M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 535
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Rev.
REVISION HISTORY
Date
Page
291
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309
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313
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368
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371
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381
383
• Table 22.9 Single-Phase Waveform Output Mode Specifications Setting
• Figure 22.16 Single-Phase Waveform Output Mode Setting value of registers
• Table 22.10 Phase-Delayed Waveform Output Mode Specifications Setting
• Figure 22.17 Phase-Delayed Waveform Output Mode Setting value of regis-
• Table 22.11 SR Waveform Output Mode Specifications Setting value of the
• Figure 22.18 SR Waveform Output Mode Setting value of registers added;
• Figure 22.20 G0CR to G1CR Registers, G0RB to G1RB Registers B14 in the
• Table 22.14 Clock Settings (Group 1) Setting value of the G1PO0 register
• Table 22.16 Pin Settings (1) Registers set for P7
• Table 22.16 Pin Settings (4) Registers set for P15
• Table 22.20 UART Mode Specifications ISTxD1 and ISRxD1 Polarity Inverse
• Table 22.21 Clock Settings Input from ISCLK1 deleted; note 4 deleted
• Table 22.22 Registers to be Used and Settings UFORM bit function modified;
• Figure 22.31 Transmit Operation Figure modified
• Figure 22.32 Receive Operation Figure modified
• 22.4.3 HDLC Data Processing Mode Description modified
• Table 22.25 HDLC Processing Mode Specifications Transmit Start Condition
• Table 22.28 Registers to be Used and Settings G1PO1 register function
Programmable I/O Ports
• Figure 24.1 Programmable I/O Ports (1) P15
• Figure 24.3 Programmable I/O Ports (3) P15 deleted; P15
• Figure 24.5 PD0 to PD15 Register Note 2 modified
• Figure 24.6 P0 to P15 Register Note 1 modified
• Figure 24.15 PUR0 Register, PUR1 Register and PUR2 Register Note 1 each
• Figure 24.17 PCR Register and IPS Register Note 1 added to the PCR register
value of the G1PO0 register changed
added; condition added
value of the G1PO0 register changed
ters added; condition added
G1PO0 register changed
condition added
G0RB to G1RBregisters changed to PER bit
changed
function deleted
CSS3 to CSS2 bit functions modified
and Receive Start Condition brought together to Data Processing Start Condition
modified
P15
added to the PUR0 Register and PUR1 Register
7
added
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
C-16
Description
Summary
0
and P15
6
0
and P7
and P15
1
7
0
deleted; P15
deleted
1
added
deleted
2
and
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