M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 349

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
. v
J
2
0
C
1
9
8 /
0 .
B
0
3
23.1.1.4 TSPRE1, TSPRE0 Bits
23.1.1.5 TSRESET Bit
23.1.1.6 ECRESET Bit
5
0
The TSPRE1 and TSPRE0 bits determine which count source is used for the time stamp counter.
When the TSRESET bit is set to "1", the CiTSR register is set to "0000
automatically set to "0" after the CiTSR register is set to "0000
When the ECRESET bit is set to "1", the CiTEC and CiREC registers are set to "00
module forcibly goes into an error active state.
The ECRESET bit is automatically set to "0" after the CAN module enters an error active state.
G
3
NOTES:
NOTES:
NOTES:
J
7
u
o r
0 -
. l
1. Change the BASICCAN bit setting only when the STATE_RESET bit is set to "1" (CAN module
2. The message slot 14 is the first slot to become active after the RESET1 and RESET0 bits are
3. The message slots 0 to 13 are not affected by entering BasicCAN mode.
1. Change the TSPRE1 and TSPRE0 bit settings only when the STATE_RESET bit is set to "1"
1. In an error active state, the CAN module is ready to communicate when 11 continuous reces-
2. The CANi
u
0
1
p
reset completed).
set to "0".
(CAN module reset completed).
sive bits are detected on the CAN bus.
CAN bus error may occur when setting the ECRESET bit to "1" during CAN frame transmission.
, 1
0
3
(
2
M
0
3
0
2
5
C
8 /
Page 324
OUT
, 5
M
pin provides an "H" signal output as soon as the ECRESET bit is set to "1". The
3
2
C
f o
8 /
4
5
9
) T
4
16
".
16
". The TSRESET bit is
23. CAN Module
16
". The CAN