M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 389

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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R
R
23.3 Timing with CAN-Associated Registers
e
E
3
. v
J
2
Figure 23.37 Example of CAN Module Reset Operation
0
C
23.3.1 CAN Module Reset Timing
23.3.2 CAN Transmit Timing
1
9
0 .
8 /
B
Figure 23.37 shows an operation example of when the CAN module is reset.
Figure 23.38 shows an operation example of when the CAN transmits a frame.
0
3
5
0
(1) The CAN module can be reset when the STATE_RESET bit in the CiSTR register (i=0,1) is set to "1"
(2) Set necessary CAN-associated registers.
(3) CAN communication can be established after the STATE_RESET bit is set to "0" (resetting) after
(1) When the TRMREQ bit in the CiMCTLj register (j=0 to 15) is set to "1" (request to transmit the data
(2) After a CAN frame transmission is completed, the SENTDATA bit in the CiMCTLj register is set to "1"
3
G
J
7
u
o r
0 -
. l
(CAN module reset completed) after the RESET1 and RESET0 bits in the CiCTLR0 register are set to
"1" (CAN module reset).
the RESET1 and RESET0 bits are set to "0" (CAN module reset exited) .
frame) while the CAN bus is in an idle state, the TRMACTIVE bit in the CiMCTLj register is set to
"1" (during transmission) and the TRMSTATE bit in the CiSTR register is set to "1" (during trans-
mission). The CAN starts transmitting the frame.
(already transmitted), the TRMSUCC bit in the CiSTR register to "1" (transmission completed) and the
SISj bit in the CiSISTR register to "1" (interrupt requested). The MBOX3 to MBOX0 bits in the CiSTR
register store transmitted message slot numbers.
RESET1 bit
STATE_RESET bit
u
RESET0 bit
0
1
p
, 1
0
3
(
2
M
0
3
0
2
5
C
8 /
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"1"
"1"
"0"
"1"
"0"
"0"
3
2
C
f o
Set to "1" by program
simultaneously
8 /
4
5
9
) T
4
Verify the STATE_RESET bit
Operation (1)
Initial Setting for the CAN
Module
Operation (2)
Verify the STATE_RESET bit
Set to "0" by program
simultaneously
Operation (3)
CAN Operation
23. CAN Module