M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 360

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
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J
2
Figure 23.12 C0REC and C1REC Registers
Figure 23.11 C0TEC and C1TEC Registers
0
C
1
23.1.9 CANi Transmit Error Count Register (CiTEC Register)
23.1.10 CANi Receive Error Count Register (CiREC Register)
9
8 /
0 .
B
0
3
5
0
G
In an error active or an error passive state, a counting value of the reception error is stored into the
CiREC register. The counter is decremented when the CAN module has received data as expected
or it is incremented when a receive error occurs.
The CiREC register is set to 127 when the CiREC register is 128 (error passive state) or more and
the CAN module has received as expected.
In a bus-off state, an indeterminate value is stored into the CiREC register. The CiREC register is set
to "00
3
J
In an error active or an error passive state, the counting value of a transmission error is stored into
the CiTEC register. The counter is decremented when the CAN module has transmitted data as
expected or is incremented when an transmit error occurs.
In a bus-off state, an indeterminate value is stored into the CiTEC register. The CiTEC register is set
to "00
7
u
o r
0 -
. l
CANi Transmit Error Count Register
CANi Receive Error Count Register
b7
b7
u
NOTES:
0
1
p
, 1
0
NOTES:
16
1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
16
3
(
2
M
" when the CAN module is placed in an error active state again.
reset and supplying the clock to the CAN module.
" when the CAN module is placed in an error active state again.
1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
0
3
0
reset and supplying the clock to the CAN module.
2
5
C
8 /
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M
3
2
C
b0
b0
f o
8 /
4
5
Counter value of transmission errors
Counter value of receive error
9
) T
4
Symbol
C0TEC
C1TEC
Symbol
C0REC
C1REC
Address
020A
028A
Address
020B
028B
16
16
(i=0, 1)
16
16
(i=0, 1)
Function
Function
After Reset
00
00
After Reset
00
00
16
16
16
16
(i=0, 1)
(i=0, 1)
(1)
(1)
23. CAN Module
RW
RO
RW
RO