M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 528

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Rev.
REVISION HISTORY
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• Figure 16.10 Transmit and Receive Operation (2) Receive Timing modified
• Table 16.9 Pin Settings in UART (2) modified
• Table 16.21 Pin Settings in Special Mode 2 (2) modified
• Table 16.27 Pin Settings in CGI Mode (2) modified
• Figure 16.29 SIM Interface Operation modified
A/D Converter
• Table 17.1 A/D Converter Specifications Explanation for A/D Conversion
• Figure 17.2 AD0CON0 Register Note 5 modified
• Table 17.2 One-shot Mode Specifications Explanation for Start Condition
• Figure 16.29 Trigger Select Function Settings modified; Note 2 added
Intelligent I/O
• Figure 21.3 G1TB Register and G1BCR0 Register Note 2 added to G1BT
• Figure 21.4 G1BCR1 Register Note 3 revised
• Figure 21.6 G1TM0 to G1TM7 Registers and G1POCR0 to G1POCR7
• Table 21.2 Base Timer Specificaitons Conditions added to Base Timer Reset
• Figure 21.12 Base Timer Operation in Two-phase Signal Processing Mode
• Table 21.5 Pin Settings for Time Measurement Function modified
• Figure 21.15 Prescaler Function and Gate Function
• Table 21.7 Pin Settings for Waveform Generation Function modified
• Table 21.9 Single-phase Waveform Output Mode Specfications Specifica-
• Figure 21.16 Single-Phase Waveform Output Mode modified
• Table 21.10 Phase-Delayed Waveform Output Mode Specifications Specifi-
• Figure 21.17 Phase-Delayed Waveform Output Mode modified
• Table 21.11 SR Waveform Output Mode Specifications Specifications for
• Figure 21.18 SR Waveform Output Mode modified
• Figure 21.20 G0CR to G1CR Registers, G0RB to G1RB Registers modified
• Figure 21.23 G0EMR to G1EMR Registers Note 1 revised
• Figure 21.24 G0ETC to G1ETC Registers Note 1 revised
• Figure 21.26 G0IRF Register Notes 1 and 2 revised
Start Condition revised; Note 2 revised
revised
register
Registers modified
Condition; Explanation for Counter increment/decrement mode in Selectable
Function revised
Figure modified; Note 1 revised; Note 2 added
tions for Output Waveform revised; Note 2 added
cations for Output Waveform modified
Output Waveform modified; Notes 3, 4, 5 added
M32C/85 Group(M32C/85, M32C/85T) Hardware Manual
C-9
Description
Summary