M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 350
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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2
Figure 23.4 C0CTLR1 and C1CTLR1 Registers
0
C
23.1.2 CANi Control Register 1 (CiCTLR1 Register)
1
9
8 /
0 .
B
0
3
5
23.1.2.1 BANKSEL Bit
23.1.2.2 INTSEL Bit
0
G
The BANKSEL bit in the C0CTLR1 register selects the registers allocated to addresses 0220
023F
to 02BF
The CiSSCTLR register, CiSSSTR register and the CiMCTL0 to CiMCTL15 registers can be ac-
cessed by setting the BANKSEL bit to "0". The CiGMR0 to CiGMR4 registers, CiLMAR0 to CiLMAR4
registers and CiLMBR0 to CiLMBR4 registers can be accessed by setting the BANKSEL bit to "1".
The INTSEL bit determines whether the three types of interrupt outputs (CANi transmit interrupt,
CANi receive interrupt and CANi error interrupt) are provided via OR or is separately.
Refer to 23.4 CAN Interrupts for details.
3
J
NOTES:
7
u
o r
0 -
. l
1. Change the INTSEL bit setting when the STATE_RESET bit is set to "1" (CAN module reset
CANi Control Register 1
b7
u
0
1
p
NOTES:
16
completed).
, 1
0
b6
3
(
. The BANKSEL bit in the C1CTLR1 register selects registers allocated to addresses 02A0
1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
2
M
16
0
b5
0
reset and supplying the clock to the CAN module.
3
0
.
2
5
C
b4
0
8 /
Page 325
b3
, 5
b2
0
M
3
b1
2
C
f o
b0
8 /
4
5
BANKSEL
Symbol
(b1 - b0)
(b5 - b4)
9
INTSEL
) T
4
Bit
(b2)
(b7)
Symbol
C0CTLR1
C1CTLR1
(i=0, 1)
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Reserved Bit
CANi Bank Switch Bit
Reserved Bit
CANi Interrupt Mode
Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Address
0241
0251
16
16
Set to "0"
0: Selects the message slot control
1: Selects the mask register
Set to "0"
0: Outputs 3 types of interrupts via OR
1: Outputs 3 types of interrupts separately
register and single-shot register
(i=0, 1)
After Reset
X000 00XX
X000 00XX
Function
(1)
2
2
23. CAN Module
RW
RW
RW
RW
RW
16
16
to
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