M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 348

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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23.1.1.1 RESET1 and RESET0 Bits
23.1.1.2 LOOPBACK Bit
23.1.1.3 BASICCAN Bit
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When both RESET1 and RESET0 bits are set to "1" (CAN module reset), the CAN module is imme-
diately initialized regardless of ongoing CAN communication.
After the RESET1 and RESET0 bits are set to "1" and the CAN module reset is completed, the
CiTSR register (i=0, 1) is set to "0000
STATE_ERRPAS and STATE_BUSOFF bits in the CiSTR register are set to "0" as well.
When both RESET1 and RESET0 bit settings are changed "1" to "0", the CiTSR register starts
counting. CAN communication is available after 11 continuous recessive bits are detected.
When the LOOPBACK bit is set to "1" (loopback function enabled) and the receive message slot has
a matched ID and frame format with a transmitted frame, the transmitted frame is stored to the
receive message slot.
When the BASICCAN bit is set to "1", the message slots 14 and 15 enter BasicCAN mode.
In BasicCAN mode, the message slots 14 and 15 are used as dual-structured buffers. The message
slots 14 and 15 alternately store a received frame having matched ID detected by acceptance filtering.
ID in the message slot 14 and the CiLMAR0 to CiLMAR4 registers are used for acceptance filtering
when the message slot 14 is active (the next received frame is to be stored in the message slot 14).
ID in the message slot 15 and the CiLMBR0 to CiLMBR4 registers are used when the message slot
15 is active. Both data frame and remote frame can be received.
Use the following procedure to enter BasicCAN mode.
(1) Set the BASICCAN bit to "1".
(2) Set the same value into IDs in the message slots 14 and 15.
(3) Set the same value in the CiLMAR0 to CiLMAR4 registers and CiLMBR0 to CiLMBR4 registers.
(4) Set the IDE14 and IDE15 bits in the CiIDR register to select a frame format (standard or ex-
(5) Set the CiMCTL14 and CiMCTL15 registers in the message slots 14 and 15 to receive the data
3
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NOTES:
NOTES:
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1. Set the same value in both RESET1 and RESET0 bits simultaneously.
2. Confirm that the STATE_RESET bit in the CiSTR register is set to "1" (CAN module reset
3. The CAN
4. For CAN communication, set the PS1, PS2, PS3, PSL1, PSL2, PSL3, PSC, PSC2, PSC3, IPS,
1. No ACK for the transmitted frame is returned.
2. Change the LOOPBACK bit setting only when the STATE_RESET bit is set to "1" (CAN module
u
tended) for the message slots 14 and 15. (Set to the same format.)
frame.
0
1
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completed) after setting the RESET1 and RESET0 bits to "1".
set to "1". CAN bus error may occur when the RESET1 and RESET0 bits are set to "1" while the
CAN frame is transmitting.
IPSA, PD7, PD8 and PD9 registers when the STATE_RESET bit is set to "1" (CAN module
reset completed).
reset completed).
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pin puts in a high-level ("H") signal as soon as the RESET1 and RESET0 bits are
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4
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16
". The CiTEC and CiREC registers are set to "00
23. CAN Module
16
" and the