M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 166

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 13.6 Transfer Cycle Examples with the Source-Read Bus Cycle
0
C
1
9
8 /
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B
0
3
5
0
G
3
J
7
u
o r
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(1) When 8-bit data is transferred
(2) When 16-bit data is transferred from an odd source address
(3) When one wait state is inserted into the source-read bus cycle under the conditions in (1)
. l
(4) When one wait state is inserted into the source-read bus cycle under the conditions in (2)
u
CPU Clock
Address
Bus
RD Signal
Data bus
CPU Clock
Address
Bus
RD Signal
CPU Clock
Address
Bus
RD Signal
Data Bus
CPU Clock
Address
Bus
RD Signal
Data Bus
WR Signal
WR Signal
Data Bus
WR Signal
WR Signal
CPU Clock
0
1
p
NOTES:
or when 16-bit data is transferred with a 16-bit data bus from an even source address
, 1
0
or when 16-bit data is transferred and 8-bit bus is used to access a source address
3
(
1. The above applies when the destination-write bus cycle is 2 CPU clock cycles (=1 bus cycle).
2
M
0
3
However, if the destination-write bus cycle is pleaced under these conditions, it will change to
the same timing as the source-read cycle illustrated above.
0
2
5
C
8 /
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CPU Use
CPU Use
CPU Use
CPU Use
CPU Use
M
CPU Use
CPU Use
CPU Use
3
2
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4
5
9
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4
Source
Source
Source
Source
Source
Source
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Destination
Source + 1
Destination
Source + 1
Destination
Destination
CPU Use
CPU Use
Destination
CPU Use
CPU Use
CPU Use
CPU Use
CPU Use
CPU Use
13. DMAC