M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 253

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 17.24 Transmit and Receive Timing in Master Mode (Internal Clock)
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17.4.2 Clock Phase Setting Function
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B
The CKPH bit in the UiSMR3 register (i=0 to 4) and the CKPOL bit in the UiC0 register select one of four
combinations of transfer clock polarity and phases.
The transfer clock phase and polarity must be the same between the master and the slave involved in the
transfer.
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17.4.2.1 When setting the DINC Bit to "0" (Master (Internal Clock))
17.4.2.2 When Setting the DINC Bit to "1" (Slave (External Clock))
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Figure 17.24 shows transmit and receive timing.
When the CKPH bit is set to "0" (no clock delay) and the SSi input pin is held high ("H"), the STxDi pin
is placed in a high-impedance state. When the SSi input pin becomes low ("L"), conditions to start a
serial transfer are met, but output is indeterminate. The serial transmission is synchronized with the
transfer clock. Figure 17.25 shows the transmit and receive timing.
When the CKPH bit is set to "1" (clock delay) and the SSi input pin is held high, the STxDi pin is placed
in a high-impedance state. When the SSi pin becomes low, the first data is output. The serial transmis-
sion is synchronized with the transfer clock. Figure 17.26 shows the transmit and receive timing.
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Data Output Timing
Data Input Timing
Signal Applied to
the SS Pin
Clock Output
(CKPOL=0, CKPH=0)
Clock Output
(CKPOL=1, CKPH=0)
Clock Output
(CKPOL=0, CKPH=1)
Clock Output
(CKPOL=1, CKPH=1)
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3
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2
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3
0
2
5
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"H"
"L"
"H"
"L"
8 /
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
4
5
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4
D
0
_____
D
1
D
_____
2
_____
D
3
_____
D
4
D
5
17. Serial I/O (Special Function)
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