M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 110

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
. v
J
2
Figure 9.6 TCSPR and CPSRF Registers
0
C
1
9
8 /
0 .
B
0
3
5
0
G
3
J
7
u
o r
0 -
. l
Clock Prescaler Reset Flag
Count Source Prescaler Register
b7
b7
u
NOTES:
0
1
p
, 1
0
b6
b6
3
1. Rewrite the CNT3 to CNT0 bits after the CST bit is set to "0".
2. Value of the TCSPR register is not reset by software reset or watchdog timer reset.
(
2
M
b5
0
b5
3
0
2
5
b4
b4
C
8 /
b3
Page 85
b3
, 5
b2
b2
M
3
b1
b1
2
C
b0
b0
f o
8 /
4
5
(b6 - b0)
(b6 - b4)
Symbol
9
CPSR
) T
Symbol
CNT0
CNT1
CNT2
CNT3
CST
4
Bit
Bit
Symbol
CPSRF
Symbol
TCSPR
Clock Prescaler Reset
Flag
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Division Rate
Select Bit
Reserved Bit
Operation Enable Bit
Bit Name
Bit Name
(1)
Address
0341
Address
035F
16
16
When the CPSR bit is set to "1", f
divided by 32 is reset.
When read, its content is "0".
If setting value is n, f
main clock, on-chip oscillator clock
or PLL clock divided by 2n.
When n is set to "0", no division is
selected.
0: Divider stops
1: Divider starts
When read,
its content is indeterminate
After Reset
0XXX XXXX
After Reset
0XXX 0000
Function
Function
2n
(2)
2
2
is the
9. Clock Generation Circuit
C
RW
RW
RW
RW
RW
RW
RW
RW
RW
RO