M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 393

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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23.4.2.2 When the INTSEL Bit is Set to "1"
1
If the CAN-associated interrupt is generated by one of the interrupt request source listed in 23.3.2
CANij Interrupts, the corresponding bit in the CiSISTR register (i=0,1) is set to "1" (interrupt re-
quested) when the CANi slot k completes a transmission or a reception. The corresponding bit in the
CiEISTR register is set to "1" (interrupt requested) when the CANi module detects a bus error, goes
into an error-passive state, or goes into a bus-off state.
The CANi receive interrupt request signal is set to "1" if the corresponding bit in the CiSIMKR register
is set to "1" (interrupt request enabled) and the corresponding bit in the CiSISTR register is set to "1"
when the CANi module completes a reception.
The CANi transmit interrupt request signal is set to "1" if the corresponding bit in the CiSIMKR register
is set to "1" and the corresponding bit in the CiSISTR register is set to "1" when the CANi module
completes a transmission.
The CANi error interrupt request signal is set to "1" if corresponding bits in the CiEIMKR register are
set to "1" and the corresponding bit in the CiEISTR register is set to "1" when the CANi module detects
a bus error, goes into an error-passive state, or goes into a bus-off state.
When the CANi receive interrupt request signal changes "0" to "1", the CAN00R bit in the IIO9IR
register and the CAN10R bit in the IIO0IR registers are set to "1" (interrupt requested). If the CAN00E
in the IIO9IE register is set to "1" (interrupt enabled), the IR bit in the CAN0IC register is set to "1"
(interrupt requested). If the CAN10E bit in the IIO0IE register is set to "1" (interrupt enabled), the IR bit
in the CAN3IC register is set to "1" (interrupt requested).
When the CANi transmit interrupt request signal changes "0" to "1", the CAN01R bit in the IIO10IR
register and the CAN11R bit in the IIO1IR registers are set to "1" (interrupt requested). If the CAN01E
in the IIO10IE register is set to "1" (interrupt enabled), the IR bit in the CAN1IC register is set to "1"
(interrupt requested). If the CAN11E bit in the IIO1IE register is set to "1" (interrupt enabled), the IR bit
in the CAN4IC register is set to "1" (interrupt requested).
When the CANi error interrupt request signal changes "0" to "1", the CAN02R bit in the IIO11IR register
and CAN12R bit in the IIO5IR register are set to "1" (interrupt requested). If the CAN02E in the IIO11IE
register is set to "1" (interrupt enabled), the IR bit in the CAN2IC register is set to "1" (interrupt re-
quested). If the CAN12E bit in the IIO5IE register is set to "1" (interrupt enabled), the IR bit in the
CAN5IC register is set to "1" (interrupt requested).
The CANi error interrupt request signal remains set to "1" if another interrupt request causes the
corresponding bit in the CiEIMKR register is set to "1" and the corresponding bit in the CiEISTR to be
set to "1" after the CANi error interrupt request signal changes "0" to "1". The CAN02R, CAN12R and
IR bits also remain unchanged.
Bits in the CiSISTR or CiEISTR register and CANijR bits (i=0,1, j=0 to 2) in the IIO0IR to IIO1IR, IIO5IR
or IIO9IR to IIO11IR registers are not set to "0" automatically, interrupt acknowledgment notwithstand-
ing. Set these bits to "0" by program.
The CANi receive interrupt and CANi transmit interrupt are acknowledged when the CAN00R bit in the
IIO9IR register, the CAN01R bit in the IIO10IR register, the CAN10R bit in the IIO0IR register and the
CAN11R bit in the IIO1IR register are set to "0". Corresponding bits in the CiSISTR register can be set
to either "0" or "1".
The CANi error interrupt is acknowledged when the CAN02R bit in the IIO11IR register, the CAN12R
bit in the IIO5IR register and corresponding bits in the CiEISTR register are set to "0".
If these bits remain set to "1", all CAN-associated interrupt request source become invalid.
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23. CAN Module