M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 172

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M
R
R
e
E
3
. v
J
2
Table 14.2 DMAC II Index Configuration in Transfer Mode
Figure 14.3 MOD
Chained Transfer
End-of-Transfer
Interrupt
Transfer Data
0
DMAC II
Index
C
1
9
0 .
8 /
B
0
3
5
0
3
G
J
7
u
o r
b15
0 -
. l
Transfer Mode (MOD)
u
0
1
NOTES:
p
, 1
0
3
(
1. MOD must be located on the RAM.
2. When the MULT bit is set to "0" (no multiple transfer), bits 6 to 4 becomes the INTE, OPER and BRST
2
M
Not Used
Not Used
COUNT
8 bytes
0
DADR
SADR
MOD
bits. When the MULT bit is set to "1" (multiple transfer), bits 6 to 4 becomes the CNT2 to CNT0 bits.
3
0
2
5
C
b8
8 /
b7
Page 147
Memory-to-Memory Transfer
/Immediate Data Transfer
, 5
Not Used
12 bytes
M
COUNT
CADR0
CADR1
DADR
SADR
Used
MOD
3
2
C
f o
b0
8 /
4
5
CNT0
(b14 - b8)
Symbol
CNT1
CNT2
OPER/
CHAIN
9
UPDS
UPDD
BRST/
MULT
Not Used
) T
INTE/
SIZE
12 bytes
IMM
4
COUNT
Bit
DADR
IADR0
IADR1
Used
SADR
MOD
(2)
(1)
(2)
(2)
Transfer Unit
Select Bit
Transfer Data
Select Bit
Transfer Source
Direction Select Bit
Transfer Destination
Direction Select Bit
Calculation Transfer
Function Select Bit
Burst Transfer
Select Bit
End-of-Transfer
Interrupt Select Bit
Chained Transfer
Select Bit
Multiple Transfer
Select Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
16 bytes
COUNT
CADR0
CADR1
SADR
DADR
IADR0
IADR1
Used
Used
MOD
Not Used
Not Used
10 bytes
COUNT
OADR
SADR
DADR
MOD
0: 8 bits
1: 16 bits
0: Immediate data
1: Memory
0: Fixed address
1: Forward address
0: Fixed address
1: Forward address
0: Not used
1: Used
0: Single transfer
1: Burst transfer
0: Interrupt not used
1: Use interrupt
0: Chained transfer not used
1: Use chained transfer
0: Multiple
transfer not used
(MULT=0)
Function
Not Used
14 bytes
COUNT
CADR0
CADR1
OADR
Calculation Transfer
SADR
DADR
Used
MOD
Not Used
14 bytes
COUNT
OADR
SADR
DADR
IADR0
IADR1
b6 b5 b4
Set to "1"
0 0 0: Do not set
0 0 1: Once
0 1 0: Twice
1 1 0: 6 times
1 1 1: 7 times
1: Use multiple
Used
MOD
Set to "0"
transfer
:
:
(MULT=1)
Function
to this value
18 bytes
COUNT
CADR0
CADR1
SADR
DADR
IADR0
IADR1
OADR
MOD
Used
Used
Multiple Transfer
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
i=1 to 7
max. 32 bytes
(when i=7)
Not Available
Not Available
COUNT
SADR1
DADR1
14. DMACII
DADRi
SADRi
MOD