M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 364
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
3
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J
2
Figure 23.15 C0EIMKR and C1EIMKR Registers
0
C
23.1.13 CANi Error Interrupt Mask Register (CiEIMKR Register)
1
9
8 /
0 .
B
Refer to 23.4 CAN Interrupt for details.
0
3
5
23.1.13.1 BOIM Bit
23.1.13.2 EPIM Bit
23.1.13.3 BEIM Bit
The BOIM bit determines whether an interrupt request is enabled or disabled when the CAN module is
placed in a bus-off state. When the BOIM bit is set to "1", the bus-off interrupt request is enabled.
The EPIM bit determines whether an interrupt request is enabled or disabled when the CAN module is
placed in an error passive state. When the EPIM bit is set to "1", the error passive interrupt request is
enabled.
The BEIM bit determines whether an interrupt request is enabled or disabled when a CAN bus error
occurs. When the BEIM bit is set to "1", the CAN bus error interrupt request is enabled.
0
G
3
J
7
u
o r
0 -
. l
CANi Error Interrupt Mask Register
b7
u
0
1
NOTES:
p
, 1
0
b6
3
1. Value is obtained by setting the SLEEP bit in the CiSLPR register to "1" (sleep mode exited) after
(
2
M
0
b5
reset and supplying the clock to the CAN module.
3
0
2
5
b4
C
8 /
Page 339
b3
, 5
b2
M
3
b1
2
C
b0
f o
8 /
4
5
(b7 - b3)
Symbol
9
) T
BOIM
EPIM
BEIM
4
Bit
Symbol
C0EIMKR
C1EIMKR
Bus-Off Interrupt
Mask Bit
Error-Passive Interrupt
Mask Bit
CAN Bus-Error Interrupt
Mask Bit
Nothing is assigned. When write, set to "0".
When read, its content is indeterminate.
Bit Name
Address
0214
0294
(i=0, 1)
16
16
0: Masks (disables) an interrupt request
1: Enables an interrupt request
0: Masks (disables) an interrupt request
1: Enables an interrupt request
0: Masks (disables) an interrupt request
1: Enables an interrupt request
After Reset
XXXX X000
XXXX X000
Function
(1)
2
2
(i=0, 1)
23. CAN Module
RW
RW
RW
RW
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