M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 390

• Manufacturer Part Number: M30853FJGP#U3
• Description: IC M32C MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30853FJGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Figure 23.39 Example of CAN Data Frame Receive Operation
Figure 23.38 Example of CAN Data Frame Transmit Operation
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C
23.3.3 CAN Receive Timing
1
9
8 /
0 .
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Figure 23.39 shows an operation example of when the CAN receives a frame.
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3
5
0
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3
(1) When the RECREQ bit in the CiMCTLj register (i=0,1, j= 0 to 15) is set to "1" (receive requested),
(2) When the CAN starts receiving the frame, the RECSTATE bit in the CiSTR register is set to "1"
(3) After the CAN frame reception is completed, the INVALDATA bit in the CiMCTLj register is set to
(4) After data is written to the message slot, the INVALDATA bit is set to "0" (storing receiving data)
J
7
u
o r
0 -
. l
NEWDATA bit
INVALDATA bit
RECSUCC bit
CAN bus
RECREQ bit
MBOX3 to
MBOX0 bits
RECSTATE bit
SISj bit
j=0 to 15
the CAN is ready to receive the frame at anytime.
(during reception).
"1" (storing received data), the NEWDATA bit in the CiMCTLj register is set to "1" (receive com-
plete) and the RECSUCC bit in the CiSTR register is set to "1" (reception completed).
and the SISj bit in the CiSISTR register is set to "1" (interrupt requested). The MBOX3 to MBOX0
bits in the CiSTR register store received message slot numbers.
CAN bus
TRMSUCC bit
TRMREQ bit
MBOX3 to
MBOX0 bits
TRMSTATE bit
SISj bit
j=0 to 15
u
SENTDATA bit
TRMACTIVE bit
0
1
p
, 1
0
3
(
2
M
0
3
0
2
5
C
8 /
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"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
M
Bus idle
3
Bus idle
2
C
(1)
Start transmtting
f o
8 /
4
5
Set to "1" by program
9
) T
4
(1)
Start
receiving
(2)
Set to "1" by program
Receive frame
Transmit frame
Receive frame
Transmit frame
Reception
completed
Transmission completed
(3)
(2)
(4)
Transmission-completed
message slot number
Reception-completed
message slot number
Intermission field
Intermission field
Bus idle
Bus idle
23. CAN Module