M30853FJGP#U3 Renesas Electronics America, M30853FJGP#U3 Datasheet - Page 160
![IC M32C MCU FLASH 100LQFP](/photos/12/22/122251/m30853fjgp_u3_sml.jpg)
M30853FJGP#U3
Manufacturer Part Number
M30853FJGP#U3
Description
IC M32C MCU FLASH 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M32C/80r
Datasheets
1.M3087BFLGPU3.pdf
(364 pages)
2.M30853FHFPD5.pdf
(94 pages)
3.M30853FHFPU3.pdf
(544 pages)
Specifications of M30853FJGP#U3
Core Processor
M32C/80
Core Size
16/32-Bit
Speed
32MHz
Connectivity
CAN, I²C, IEBus, SIO, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30853FJGP#U3M30853FJGP#D5
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M
R
R
e
E
3
. v
J
2
Figure 13.2 DM0SL to DM3SL Registers
0
C
1
9
8 /
0 .
B
0
3
5
0
G
3
J
7
u
o r
0 -
. l
DMAi Request Source Select Register
b7
u
NOTES:
0
1
p
, 1
0
b6
1. Change the DSEL4 to DSEL0 bit settings while the MDi1 and MDi0 bits in the DMD0 and DMD1
2. When the DSR bit is set to "1", set the DRQ bit to "1" simultaneously.
3. Do not set the DRQ bit to "0".
3
(
2
M
registers are set to "00
DSEL4 to DSEL0 bit settings are changed.
0
b5
3
0
2
5
e.g., MOV.B #083h, DMiSL ; Set timer A0
e.g., OR.B #0A0h, DMiSL
b4
C
8 /
Page 135
b3
, 5
b2
M
3
b1
2
C
b0
f o
8 /
4
5
2
Symbol
9
DSEL0
DSEL1
DSEL2
DSEL3
DSEL4
) T
" (DMA disabled). Also, set the DRQ bit to "1" simultaneously when the
DRQ
DSR
(b6)
4
Bit
Symbol
DM0SL to DM3SL 0378
DMA Request Source
Select Bit
Software DMA
Request Bit
Reserved Bit
DMA Request Bit
Bit Name
(1)
(2)
Address
16,
(2, 3)
0379
(i=0 to 3)
16,
037A
See Table 13.2 for the DMiSL
register (i = 0 to 3) function
When a software trigger is selected,
a DMA request is generated by
setting this bit to "1" (When read, its
content is always "0")
0 : Not requested
1 : Requested
When read,
its content is indeterminate
16,
037B
16
Function
After Reset
0X00 0000
2
RW
RW
RW
RW
RW
RW
RW
RW
RO
13. DMAC
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