SAK-C161CS-LF CA Infineon Technologies, SAK-C161CS-LF CA Datasheet - Page 15

• Manufacturer Part Number: SAK-C161CS-LF CA
• Description: IC MCU 16BIT 256KB TQFP-128-2
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C161CS-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 93
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 128-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: K161CSLFCANP; K161CSLFCAXT; SAK-C161CS-LFCA; SAK-C161CS-LFCAINTR; SAK-C161CS-LFCATR; SAK-C161CS-LFCATR; SAKC161CSLFCAXT; SP000106869

Table 2
Symbol Pin
READY 82
ALE
EA
PORT0
P0L.0-7
P0H.0-7
Data Sheet
No.
83
84
85-
92
95-
102
Pin Definitions and Functions (cont’d)
Input
Outp.
I
O
I
IO
Function
Ready Input. When the Ready function is enabled, a high
level at this pin during an external memory access will force
the insertion of memory cycle time waitstates until the pin
returns to a low level.
An internal pullup device will hold this pin high when nothing
is driving it.
Address Latch Enable Output. Can be used for latching the
address into external memory or an address latch in the
multiplexed bus modes.
External Access Enable pin. A low level at this pin during and
after Reset forces the C161CS/JC/JI to begin instruction
execution out of external memory. A high level forces
execution out of the internal program memory.
“ROMless” versions must have this pin tied to ‘0’.
PORT0 consists of the two 8-bit bidirectional I/O ports P0L
and P0H. It is bit-wise programmable for input or output via
direction bits. For a pin configured as input, the output driver
is put into high-impedance state.
In case of an external bus configuration, PORT0 serves as
the address (A) and address/data (AD) bus in multiplexed
bus modes and as the data (D) bus in demultiplexed bus
modes.
Demultiplexed bus modes:
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7:
Multiplexed bus modes:
Data Path Width:
P0L.0 – P0L.7:
P0H.0 – P0H.7:
Note: At the end of an external reset (EA = ‘0’) PORT0 also
inputs the configuration values.
11
8-bit
D0 – D7
I/O
8-bit
AD0 – AD7
A8 - A15
16-bit
D0 - D7
D8 - D15
16-bit
AD0 - AD7
AD8 - AD15
C161CS/JC/JI-32R
C161CS/JC/JI-L
V3.0, 2001-01