SAK-C161CS-LF CA Infineon Technologies, SAK-C161CS-LF CA Datasheet - Page 84

• Manufacturer Part Number: SAK-C161CS-LF CA
• Description: IC MCU 16BIT 256KB TQFP-128-2
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C161CS-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 93
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 128-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: K161CSLFCANP; K161CSLFCAXT; SAK-C161CS-LFCA; SAK-C161CS-LFCAINTR; SAK-C161CS-LFCATR; SAK-C161CS-LFCATR; SAKC161CSLFCAXT; SP000106869

Figure 24
Notes
1)
2)
3)
4)
5)
6)
7)
Data Sheet
Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS).
The leading edge of the respective command depends on RW-delay.
READY sampled HIGH at this sampling point generates a READY controlled waitstate,
READY sampled LOW at this sampling point terminates the currently running bus cycle.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to CLKOUT
(e.g. because CLKOUT is not enabled), it must fulfill
if READY is removed in reponse to the command (see Note
Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may
be inserted here.
For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC waitstate this delay is zero.
The next external bus cycle may start here.
CLKOUT
ALE
Command
RD, WR
Sync
READY
Async
READY
CLKOUT and READY
t
58
3)
Running Cycle
t
t
34
32
t
t
59
30
2)
t
33
t
t
t
31
35
58
3)
t
37
3)
1)
5)
t
t
36
59
80
t
37
t
in order to be safely synchronized. This is guaranteed,
29
t
35
4)
Waitstate
READY
).
3)
t
36
MUX/Tristate
t
60
4)
see
C161CS/JC/JI-32R
6)
C161CS/JC/JI-L
6)
V3.0, 2001-01
MCT04447
7)