SAK-C161CS-LF CA Infineon Technologies, SAK-C161CS-LF CA Datasheet - Page 19

• Manufacturer Part Number: SAK-C161CS-LF CA
• Description: IC MCU 16BIT 256KB TQFP-128-2
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C161CS-LF CA

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 93
• Program Memory Type: ROMless
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 128-LFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: K161CSLFCANP; K161CSLFCAXT; SAK-C161CS-LFCA; SAK-C161CS-LFCAINTR; SAK-C161CS-LFCATR; SAK-C161CS-LFCATR; SAKC161CSLFCAXT; SP000106869

Functional Description
The architecture of the C161CS/JC/JI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C161CS/JC/JI.
Note: All time specifications refer to a CPU clock of 25 MHz
Figure 3
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see
The XBUS resources (XRAM, CAN, SDLM, IIC, ASC1) of the C161CS/JC/JI can be
enabled during initialization by setting the general X-Peripheral enable bit XPEN
(SYSCON.2).
If the X-Peripherals remain disabled they consume neither address space nor port pins.
Data Sheet
8
8
(see definition in the AC Characteristics section).
CAN/SDLM
400 KBd, 2 Ch.
2.0B act. / Cl.B
ProgMem
256 KByte
XRAM
(USART)
ASC1
8 KByte
ROM
IIC
Port 0
XBUS Control
Block Diagram
External Bus
16
Control
EBC
Instr. / Data
Port 1
16
16
16
32
Channels
ADC
10-Bit
12
Port 5
External Instr. / Data
12
(USART)
ASC0
BRGen
Interrupt Controller 16-Level
C166-Core
CPU
BRGen
SSC
(SPI)
15
Port 3
15
PEC
Priority
GPT
T2
T3
T4
T5
T6
Interrupt Bus
Peripheral Data Bus
Port 7
Data
Data
4
16
CCOM2
16
16
T7
T8
C161CS/JC/JI-32R
RTC
CCOM1
Osc / PLL
C161CS/JC/JI-L
Port 9
6
MCB04323_1CSR
T0
T1
2 KByte
IRAM
Internal
RAM
Figure
WDT
V3.0, 2001-01
3).
XTAL
8