Z16F2810VH20EG Zilog, Z16F2810VH20EG Datasheet - Page 136

• Manufacturer Part Number: Z16F2810VH20EG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4691-5; Z16F2810VH20EG

PWM Control Register Definitions
PS022008-0810
PWM Operation in CPU HALT Mode
PWM Operation in CPU STOP Mode
Observing the State of PWM Output Channels
The fault inputs are individually enabled through the PWM fault control register. If a fault
condition is detected and the source is enabled, the fault interrupt is generated. The
Fault Status Register (PWMFSTAT)
interrupt.
When a fault is detected and the PWM outputs are disabled, modulator control of the
PWM outputs are reenabled either by the software or by the fault input signal deasserting.
Selection of the reenable method is made using the
(PWMFCTL). Configuration of the fault modes and reenable methods allow 
pulse-by-pulse limiting and hard shutdown. When configured in AUTOMATIC
RESTART mode, the PWM outputs are re-engaged at beginning of the next PWM cycle
(master timer value is equal to 0) if all fault signals are deasserted. In software controlled
restart, all fault inputs must be deasserted and the fault flags must be cleared.
The fault input pin is Schmitt-triggered. The input signal from the pin as well as the
comparators pass though an analog filter to reject high-frequency noise.
The logic path from the fault sources to the PWM output is asynchronous ensuring that the
fault inputs forces the PWM outputs to their off-state even if the system clock is stopped.
When the ZNEO CPU is operating in HALT mode, the PWM continues to operate if it is
enabled. To minimize current in HALT mode, the PWM must be disabled by clearing the
PWMEN bit to 0.
When the ZNEO CPU is operating in STOP mode, the PWM is disabled as the system
clock ceases to operate in STOP mode. The PWM output remains in the same state as they
were prior to entering the STOP mode. In normal operation, the PWM outputs must be
disabled by software prior to the CPU entering the STOP mode. A fault condition detected
in STOP mode forces the PWM outputs to the predefined off-state.
The logic value of the PWM outputs is sampled by reading the PWMIN register. If a
PWM channel pair is disabled (option bit is not set), the associated PWM outputs are
forced to high impedance and are used as general purpose inputs.
The following sections describe the various PWM control registers.
P R E L I M I N A R Y
is read to determine which fault source caused the
PWM Fault Control Register
Multi-Channel PWM Timer
Product Specification
ZNEO
Z16F Series
PWM
121