Z16F2810VH20EG Zilog, Z16F2810VH20EG Datasheet - Page 67

• Manufacturer Part Number: Z16F2810VH20EG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4691-5; Z16F2810VH20EG

PS022008-0810
Table 16. External Interface Timing for a Read Operation - Normal Mode
Parameter
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
External Interface Read Timing - Normal Mode
Figure 13
performing a Read operation in NORMAL mode. In
the Wait state generator has been configured to provide 2 Wait states during Read
operations. For proper data hold time determination, you must know that the input data is
captured on chip during the rising edge of the system clock prior to the RD signal 
de-assertion. The Read signal (RD) timing is shown for both NORMAL and ISA modes.
Abbreviation
XIN Rise to Address Valid Delay
XIN Rise to Address Output Hold Time
Data Input Valid to XIN Rise Setup Time
RD Rise to Data Input Hold Time
XIN Rise to CS Assertion Delay
XIN Rise to CS Deassertion Hold Time
XIN Rise to RD Assertion Delay
XIN Rise to RD Deassertion Hold Time
WAIT Input Pin Assertion to XIN Rise Setup Time
WAIT Input Pin Deassertion to XIN Rise Setup Time
XIN Rise to DMAACK Assertion Delay
XIN Rise to DMAACK Deassertion Hold Time
XIN Rise to BHEN or BLEN Assertion Delay
XIN Rise to BHEN or BLEN Deassertion Hold Time
on page 53 and
Table 16
P R E L I M I N A R Y
provide timing information for the external interface
Figure 13
Minimum
on page 53, it is assumed
3
0
3
3
1
1
3
3
Product Specification
Delay (ns)
ZNEO
Maximum
External Interface
Z16F Series
10
10
10
10
10
3
52