Z16F2810VH20EG Zilog, Z16F2810VH20EG Datasheet - Page 58

• Manufacturer Part Number: Z16F2810VH20EG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4691-5; Z16F2810VH20EG

PS022008-0810
DATA[15:0]
ISA-Compatible Mode
ADDR[23:0]
(output)
controlled by the CSxWAIT[3:0] field and the PRxWAIT[1:0] field as shown in the
Select Control Registers
number of system clock cycles. A maximum of 31 Waits states are inserted. An example
of Wait state operation is illustrated in
has been configured to provide two Wait states. See the detailed timing diagrams in
External Interface Timing
Figure 10. External Interface Wait State Operation Example (Write Operation)
Configuring the external interface for ISA mode adjusts the Read timing to follow the ISA
mode commonly employed in PC and related applications. In ISA mode, assertion of the
Read signal (RD) is delayed one-half system clock. Also, an extra Wait state is added
during Read operations.
XIN
WR
CS
TCLK
on page 44. The Wait states idle the ZNEO CPU for the specified
on page 48.
P R E L I M I N A R Y
TWAIT
Figure
State Generator
Enabled in Wait
2 Wait States
10. In this example, the external interface
TWAIT
Product Specification
ZNEO
External Interface
Z16F Series
Chip
43