Z16F2810VH20EG Zilog, Z16F2810VH20EG Datasheet - Page 243

• Manufacturer Part Number: Z16F2810VH20EG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4691-5; Z16F2810VH20EG

Table 108. I
Table 109. I
I
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
2
C Control Register Definitions
I
I
2
2
C Data Register
C Interrupt Status Register
2
2
TDRE
C Data Register (I2CDATA)
C Interrupt Status Register (I2CISTAT)
R
7
7
1
The following section describes the I
The I
register to transmit onto the I
Shift register after it is received from the I
in the Register File address space, but is used only to buffer incoming and outgoing data.
Writes by software to the I2CDATA register are blocked if a slave write transaction is
underway (I
The Read-only I
current I
one or more of the
bits do not generate an interrupt but rather provide status associated with the
interrupt.
TDRE—Transmit data register empty
When the I
set, the I
2
C Data register (see
2
2
RDRF
C Controller generates an interrupt, except when the I
C interrupt and provides status of the I
2
R
6
6
0
2
C Controller is enabled, this bit is 1 if the I
C Controller in slave mode, data being received).
2
C Interrupt Status register (see
TDRE
SAM
R
5
5
0
,
RDRF
P R E L I M I N A R Y
Table
2
C bus. This register also holds data that is loaded from the
,
SAM
108) holds the data that is to be loaded into the Shift
GCA
R
4
4
0
,
2
FF-E240H
FF-E241H
C Control registers.
ARBLST
DATA
R/W
0
2
C bus. The I
,
RD
R
3
SPRS
3
0
2
Table
C Controller
or
109) indicates the cause of any
2
2
ARBLST
C Data register is empty. When
NCKI
C Shift register is not accessible
R
2
2
0
.
I
bits is set
2
When an interrupt occurs
2
C Controller is shifting in
C Master/Slave Controller
Product Specification
ZNEO
SPRS
R
1
1
0
.
The
Z16F Series
SAM
GCA
NCKI
bit
and
R
0
0
0
RD
,
227