Z16F2810VH20EG Zilog, Z16F2810VH20EG Datasheet - Page 318

• Manufacturer Part Number: Z16F2810VH20EG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4691-5; Z16F2810VH20EG

Table 165. OCD Baud Rate Limits
PS022008-0810
System Clock
Frequency
20.0 MHz
1.0 MHz
Baud Rate Generator
If the stop bit is High, the data was correctly framed between a start and stop bit. After the
receiver samples the middle of the stop bit, it begins searching for another start bit. The
receiver does not wait for the full stop bit to be received before searching for the next start
bit. This is to correct for any bit skew due to error between the transmit and receive baud
rate clocks.
The baud rate generator (BRG) is used to generate a bit clock for transmit and receive
operations. The BRG reload register is automatically configured by the auto-baud 
detector, or it is written by software.
The value in the BRG reload register is calculated as:
This reload value is the number of system clocks used to transmit and receive eight data
bits.
The BRG has a 16-bit reload counter and is clocked by the system clock. When the OCD
is enabled, this register is limited to 12 bits. The minimum baud rate is calculated using the
following equation:
The minimum baud rate when the OCD is enabled is the system clock frequency divided
by 512. The minimum baud rate is the system clock frequency divided by 8192 when the
OCD is disabled.
For asynchronous operation, the maximum baud rate is roughly the system clock 
frequency divided by eight (eight clocks per bit). With slow baud rates and clean signals,
you will be able to achieve asynchronous baud rates up to 4 clocks per bit. If data is 
synchronized with the system clock, the maximum baud rate is the system clock frequency
(one bit per clock). The maximum baud rates are limited by the rise and fall times due to
the cable impedance.
crystal frequencies.
BAUD RELOAD VALUE =
BAUD RELOAD VALUE =
2.5 M baud
Baud Rate
125 k baud
Maximum
Table 165
P R E L I M I N A R Y
*
lists minimum and maximum baud rates for sample 
Minimum Baud Rate
SYSTEM CLOCK
SYSTEM CLOCK
BAUD RATE
BAUD RATE
(OCDEN=0)
2442 baud
123 baud
x 8
x 8
Product Specification
Minimum Baud Rate
ZNEO
39,062 baud
(OCDEN=1)
On-Chip Debugger
1953 baud
Z16F Series
302