M30833FJFP#U5 Renesas Electronics America, M30833FJFP#U5 Datasheet - Page 227

• Manufacturer Part Number: M30833FJFP#U5
• Description: IC M32C/83 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30833FJFP#U5

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 31K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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16.3.3 Arbitration
16.3.4 Transfer Clock
16.3.5 SDA Output
1
9
C
3 .
B
The ABC bit in the UiSMR register (i=0 to 4) determines an update timing for the ABT bit in the UiRB
register. On the rising edge of SCLi, the microcomputer determines whether a transmit data matches
data input to the SDAi pin.
When the ABC bit is set to "0" (update per bit), the ABT bit is set to "1" as soon as a data discrepancy is
detected. The ABT bit is set to "0" if not detected. When the ABC bit is set to "1", the ABT bit is set to "1"
(detected-arbitration is lost) on the falling edge of the ninth bit of the transfer clock if any discrepancy is
detected. When the ABT bit is updated per byte, set the ABT bit to "0" (not detected-arbitration is won)
between an ACK detection in the first byte data and the next byte data to be transferred. When the ALS
bit in the UiSMR2 register is set to "1" (SDA output stop enabled), the arbitration lost occurs. As soon as
the ABT bit is set to "1", the SDAi pin is placed in a high-impedance state.
The transfer clock transmits and receives data as is shown in Figure 16.22
The CSC bit in the UiSMR2 register (i=0 to 4) synchronizes an internally generated clock (internal SCLi)
with the external clock applied to the SCLi pin. When the CSC bit is set to "1" (clock synchronous en-
abled) and the internal SCLi is held high ("H"), the internal SCLi become low ("L") if signal input to the
SCLi pin is on the falling edge. Value of the UiBRG register is reloaded to start counting for low level. A
counter stops when the SCLi pin is held "L" and then the internal SCLi changes "L" to "H". Counting is
resumed when the SCLi pin become "H". The transfer clock of UARTi is equivalent to the AND for signals
from the internal SCLi and the SCLi pin.
The transfer clock is synchronized between a half cycle before the falling edge of first bit of the internal
SCLi and the rising edge of the ninth bit. Select the internal clock as the transfer clock while the CSC bit
is set to "1".
The SWC bit in the UiSMR2 register determines whether the SCLi pin is fixed to output an "L" signal on
the falling edge of the ninth cycle of the transfer clock or not.
When the SCLHI bit in the UiSMR4 register is set to "1" (enabled), a SCLi output stops when a stop
condition is detected (high-impedance).
When the SWC2 bit in the UiSMR2 register is set to "1" (0 output), the SCLi pin forcibly outputs an "L"
signal while transmitting and receiving. The fixed "L" signal applied to the SCLi pin is cancelled by setting
the SWC2 bit to "0" (transfer clock) and the transfer clock is input to and output from the SCLi pin.
When the CKPH bit in the UiSMR3 register is set to "1" and the SWC9 bit in the UiSMR4 register is set to
"1" (SCL "L" hold enabled), the SCLi pin is fixed to output an "L" signal on the next falling edge after the
ninth bit of the clock. The fixed "L" signal applied to the SCLi pin is cancelled by setting the SWC9 bit to
"0" (SCL "L" hold disabled).
Values in bits 7 to 0 (D
ninth bit (D
Set the default value of SDAi transmit output when the IICM bit is set to "1" (I
SMD0 bits in the UiMR register are set to "000
The DL2 to DL0 bits in the UiSMR3 register determine no delay in the SDAi output or a delay of 2 to 8
UiBRG register count source cycles.
When the SDHI bit in the UiSMR2 register is set to "1" (SDA output disabled), the SDAi pin is forcibly
placed in a high-impedance state. Do not set in the SDHI bit on the rising edge of the URTi transfer clock.
The ABT bit in the UiRB register may be set to "1" (detected).
8 /
0
1
0
3
3
J
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4
a
0 -
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1
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3
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1
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8
(
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) is ACK or NACK.
0
0
3
6
2
C
Page 202
8 /
, 3
7
M
to D
3
2
C
f o
0
8 /
) in the UiTB register (i=0 to 4) are output in descending order from D
4
8
3
8
) T
2
" (serial I/O disabled).
16. Serial I/O (Special Function)
2
C mode) and the SMD2 to
7
. The