AT89LP428-20AU Atmel, AT89LP428-20AU Datasheet - Page 120

• Manufacturer Part Number: AT89LP428-20AU
• Description: MCU 8051 4K FLASH SPI 32TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP428-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: AT89x
• Core: 8051
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

23.4
23.5
23.6
120
Status Register
DATA Polling
Flash Security
AT89LP428/828
The current state of the memory may be accessed by reading the status register. The status reg-
ister is shown in
Table 23-4.
The AT89LP428/828 implements DATA polling to indicate the end of a programming cycle.
While the device is busy, any attempted read of the last byte written will return the data byte with
the MSB complemented. Once the programming cycle has completed, the true value will be
accessible. During Erase the data is assumed to be FFH and DATA polling will return 7FH.
When writing multiple bytes in a page, the DATA value will be the last data byte loaded before
programming begins, not the written byte with the highest physical address within the page.
The AT89LP428/828 provides two Lock Bits for Flash Code Memory security. Lock bits can be
left unprogrammed (FFH) or programmed (00H) to obtain the protection levels listed in
5. Lock bits can only be erased (set to FFH) by Chip Erase. Lock bit mode 2 disables program-
ming of all memory spaces, including the User Signature Array and User Configuration Fuses.
User fuses must be programmed before enabling Lock bit mode 2 or 3. Lock bit mode 3 imple-
ments mode 2 and also blocks reads from the code memory; however, reads of the User
Signature Array, Atmel Signature Array, and User Configuration Fuses are still allowed.
Table 23-5.
Symbol
LOAD
SUCCESS
WRTINH
BUSY
Program Lock Bits (by address)
Mode
Bit
1
2
3
–
7
Function
Load Flag. Cleared low by the load page buffer command and set high by the next
memory write. This flag signals that the page buffer was previously loaded with data by
the load page buffer command.
Success Flag. Cleared low at the start of a programming cycle and will only be set high if
the programming cycle completes without interruption from the brownout detector (BOD).
Write Inhibit Flag. Cleared low by the BOD whenever programming is inhibited due to V
falling below the minimum required programming voltage. If a BOD episode occurs during
programming, the SUCCESS flag will remain low after the cycle is complete. WRTINH low
also forces BUSY low.
Busy Flag. Cleared low whenever the memory is busy programming or if write is currently
inhibited.
Status
Lock Bit Protection Modes
Table
FFH
00H
00H
00H
Register
23-4.
–
6
FFH
FFH
01H
00H
–
5
Protection Mode
No program lock features
Further programming of the Flash is disabled
Further programming of the Flash is disabled and verify (read)
is also disabled; OCD is disabled
–
4
LOAD
3
SUCCESS
2
WRTINH
1
3654A–MICRO–8/09
BUSY
0
Table 23-
CC