AT89LP428-20AU Atmel, AT89LP428-20AU Datasheet - Page 70

MCU 8051 4K FLASH SPI 32TQFP

AT89LP428-20AU

Manufacturer Part Number
AT89LP428-20AU
Description
MCU 8051 4K FLASH SPI 32TQFP
Manufacturer
Atmel
Series
89LPr
Datasheet

Specifications of AT89LP428-20AU

Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
AT89x
Core
8051
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89LP428-20AU
Manufacturer:
RFMD
Quantity:
1 240
Part Number:
AT89LP428-20AU
Manufacturer:
Atmel
Quantity:
10 000
13.4.2
70
AT89LP428/828
Symmetrical PWM
Figure 13-8. Asymmetrical (Edge-Aligned) PWM
For Symmetrical PWM, Timer 2 should be configured for Auto-reload mode and Count Mode 2
or 3 (CP/RL2 = 0, DCEN = 0, T2CM1-0 = 1xB). Symmetrical PWM uses dual-slope operation as
shown in
MIN. The timer is equal to TOP for exactly one clock cycle. In non-inverting mode, the output
CCx is cleared on the up-count compare match between Timer 2 (TL2, TH2) and the channel
data register (CCxL, CCxH), and set at the down-count compare match. In inverting mode, the
output CCx is set on the up-count compare match between Timer 2 and the data register, and
cleared at the down-count compare match. The resulting symmetrical PWM output waveform is
center-aligned around the timer equal to TOP point. Symmetrical PWM may be used to generate
non-overlapping waveforms.
The TOP value in RCAP2L and RCAP2H is double buffered such that the output frequency is
only updated at the underflow. The channel data register (CCxL, CCxH) is also double-buffered
to prevent glitches. The output frequency and duty cycle for symmetrical PWM are given by the
following equations:
The extreme compare values represent special cases when generating a PWM waveform. If the
compare value is set equal to (or greater than) TOP, the output will remain high or low for non-
inverting and inverting modes, respectively. If the compare value is set to MIN (0000H), the out-
put will remain low or high for non-inverting and inverting modes, respectively.
{RCAP2H,RCA2L}
{CCxH,CCxL}
Figure
Non-inverted
Inverted
Inverting:
13-9. The timer counts up from MIN to TOP and then counts down from TOP to
CCx
Non-Inverting:
Duty Cycle
f
OUT
=
---------------------------------------------------------------- -
2
×
Duty Cycle
Oscillator Frequency
=
{
RCAP2H RCAP2L
100%
CP/RL2 = 0, T2CM
×
=
,
{
-------------------------------------------------------------------------------------------------- -
RCAP2H RCAP2L
100%
{
×
}
RCAP2H RCAP2L
1-0
,
------------------------------------------------------
{
×
RCAP2H RCAP2L
= 01B, DCEN = 0
-------------------- -
TPS
{
CCxH CCxL
1
,
+
}
1
,
,
{
CCxH CCxL
}
}
,
}
}
3654A–MICRO–8/09

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