AT89LP428-20AU Atmel, AT89LP428-20AU Datasheet - Page 84

• Manufacturer Part Number: AT89LP428-20AU
• Description: MCU 8051 4K FLASH SPI 32TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP428-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: AT89x
• Core: 8051
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

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AT89LP428/828
Figure 16-2. Mode 0 Waveforms
Mode 0 may be used as a hardware accelerator for software emulation of serial interfaces such
as a half-duplex Serial Peripheral Interface (SPI) in mode (0,0) or (1,1) or a Two-wire Interface
(TWI) in master mode. An example of Mode 0 emulating a TWI master device is shown in
16-3. In this example, the start, stop, and acknowledge are handled in software while the byte
transmission is done in hardware. Falling/rising edges on TXD are created by setting/clearing
SM2. Rising/falling edges on RXD are forced by setting/clearing the P3.0 register bit. SM2 and
P3.0 must be 1 while the byte is being transferred.
Figure 16-3. UART Mode 0 TWI Emulation (SMOD1 = 1)
Mode 0 transfers data LSB first whereas SPI or TWI are generally MSB first. Emulation of these
interfaces may require bit reversal of the transferred data bytes. The following code example
reverses the bits in the accumulator:
Write to SBUF
SMOD1 = 0
SM2 = 0
SMOD1 = 1
SM2 = 0
SMOD1 = 0
SM2 = 1
SMOD1 = 1
SM2 = 1
(SDA) RXD
(SCL) TXD
EX:
REVRS: RLC
SM2
P3.0
TI
RXD (RX)
RXD (RX)
RXD (RX)
RXD (RX)
RXD (TX)
RXD (TX)
RXD (TX)
RXD (TX)
MOV
XCH
RRC
XCH
DJNZ R7, REVRS
TXD
TXD
TXD
TXD
R7, #8
A
A, R6
A
A, R6
0
0
0
0
0
0
0
1
0
0
; C << msb(ACC)
; msb(ACC) >> B
1
1
2
1
1
1
1
1
1
3
2
2
2
2
2
2
2
2
4
3
3
3
3
3
3
3
3
5
4
4
4
4
4
4
4
4
6
5
5
Sample ACK
5
5
5
5
5
5
7
6
6
6
6
6
6
6
6
ACK
3654A–MICRO–8/09
7
7
7
7
7
7
7
7
Figure