AT89LP428-20AU Atmel, AT89LP428-20AU Datasheet - Page 64

• Manufacturer Part Number: AT89LP428-20AU
• Description: MCU 8051 4K FLASH SPI 32TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP428-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: AT89x
• Core: 8051
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

Table 13-4.
Notes:
64
T2CCC Address = 0D4H
Not Bit Addressable
Bit
Symbol
CIENx
CDIRx
CTCx
CCMx
CxM
[2 - 0]
1. All writes/reads to/from T2CCC will access channel X as currently selected by T2CCA.The control registers for the remain-
2. Analog Comparator A events are determined by the CMA
3. Analog Comparator B events are determined by the CMB
4. Asymmetrical versus Symmetrical PWM is determined by the Timer 2 Count Mode. See
AT89LP428/828
CIENx
ing unselected channels are not accessible.
page
7
Function
Channel X Interrupt Enable. When set, channel X’s interrupt flag, CCFx in T2CCF, will generate an interrupt when
ECC = 1. Clear to disable interrupts from channel X.
Channel X Capture Direction. In dual-slope modes, a compare/capture event on channel X will store the current count
direction into CDIRx. Up-counting = 0 and down-counting = 1. Modifying this bit has no effect.
Clear Timer on Compare/Capture of Channel X. When set, the Timer 2 registers TL2 and TH2 will be cleared by a
compare/capture event on channel X. When cleared, Timer 2 is unaffected by channel X events.
Channel X Compare/Capture Mode. When CCMx = 1, channel X operates in compare mode. When CCMx = 0, channel
X operates in capture mode.
Channel X Mode. Selects the output/input events for compare/capture channel X.
CxM2
CxM2
T2CCC – Timer/Counter 2 Compare/Capture Control
68.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CDIRx
CxM1
CxM1
6
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CxM0
CxM0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–
5
Capture Event (CCMx = 0)
Disabled
Trigger on negative edge of CCx pin
Trigger on positive edge of CCx pin
Trigger on either edge of CCx pin
Trigger on Timer 0 overflow
Trigger on Timer 1 overflow
Trigger on Analog Comparator A Event
Trigger on Analog Comparator B Event
Compare Action (CCMx = 1)
Output disabled (interrupt only)
Set CCx pin on compare match
Clear CCx pin on compare match
Toggle CCx pin on compare match
Inverting Pulse Width Modulation
Non-inverting Pulse Width Modulation
Reserved
Reserved
CTCx
4
2-0
2-0
CCMx
bits in ACSRA. See
bits in ACSRB. See
3
(4)
(4)
CxM2
(2)
(3)
2
Table 18-1 on page
Table 18-2 on page
Reset Value = 00X0 0000B
“Pulse Width Modulation Mode” on
CxM1
1
103.
102.
CxM0
3654A–MICRO–8/09
0