AT89LP428-20AU Atmel, AT89LP428-20AU Datasheet - Page 26

• Manufacturer Part Number: AT89LP428-20AU
• Description: MCU 8051 4K FLASH SPI 32TQFP
• Manufacturer: Atmel
• Series: 89LPr

Specifications of AT89LP428-20AU

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 30
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-TQFP, 32-VQFP
• Processor Series: AT89x
• Core: 8051
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: AT89ISP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.3
7.4
7.5
8. Power Saving Modes
8.1
26
External Reset
Watchdog Reset
Software Reset
Idle Mode
AT89LP428/828
The P3.6/RST pin can function as either an active-low reset input or as a digital general-
purpose I/O, P3.6. The Reset Pin Enable Fuse, when set to “1”, enables the external reset input
function on P3.6. (see
used as an input or output pin. When configured as a reset input, the pin must be held low for at
least two clock cycles to trigger the internal reset. The RST pin includes an on-chip pull-up resis-
tor tied to V
Note:
When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles.
Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the
watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times
out. See
Watchdog.
The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset
sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDT-
CON. See
sequences other than 5AH/A5H or 1EH/E1H to WDTRST will generate an immediate reset and
set both WDTOVF and SWRST to flag an error.
The AT89LP428/828 supports two different power-reducing modes: Idle and Power-down.
These modes are accessed through the PCON register.
Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU
state is preserved in its entirety, including the RAM, stack pointer, program counter, program
status word, and accumulator. The Port pins hold the logic states they had at the time that Idle
was activated. Idle mode leaves the peripherals running in order to allow them to wake up the
CPU when an interrupt is generated. The timers, UART, SPI, comparators, GPI and CCA
peripherals continue to function during Idle. If these functions are not needed during idle, they
should be explicitly disabled by clearing the appropriate bits in their respective SFRs. The
watchdog may be selectively enabled or disabled during Idle by setting/clearing the WDIDLE bit.
Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an
interrupt, the interrupt will immediately be serviced, and following RETI the next instruction to be
executed will be the one following the instruction that put the device into Idle.
During a power-up sequence, the fuse selection is always overridden and therefore the pin will
always function as a reset input. An external circuit connected to this pin should not hold this
pin LOW during a power-on sequence if the pin is configured as a general I/O, as this will
keep the device in reset until the pin transitions high. After the power-up delay, this input will
function either as an external reset input or as a digital input as defined by the fuse bit. Only a
power-up reset will temporarily override the selection defined by the reset fuse bit. Other sources
of reset will not override the reset fuse bit. P3.6/RST also serves as the In-System Programming
(ISP) enable. ISP is enabled when the external reset pin is held low. When the reset pin is dis-
abled by the fuse, ISP may only be entered by pulling P3.6 low during power-up.
“Programmable Watchdog Timer” on page 105
“Software Reset” on page 106
CC
. The pull-up is disabled when the pin is configured as P3.6.
“User Configuration Fuses” on page
for more information on software reset. Writing any
for details on the operation of the
121). When cleared, P3.6 may be
3654A–MICRO–8/09