AT89LP428-20AU Atmel, AT89LP428-20AU Datasheet - Page 96

MCU 8051 4K FLASH SPI 32TQFP

AT89LP428-20AU

Manufacturer Part Number
AT89LP428-20AU
Description
MCU 8051 4K FLASH SPI 32TQFP
Manufacturer
Atmel
Series
89LPr
Datasheet

Specifications of AT89LP428-20AU

Core Processor
8051
Core Size
8-Bit
Speed
20MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
30
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
AT89x
Core
8051
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
AT89ISP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT89LP428-20AU
Manufacturer:
RFMD
Quantity:
1 240
Part Number:
AT89LP428-20AU
Manufacturer:
Atmel
Quantity:
10 000
17.4
Figure 17-3. SPI Transfer Format with CPHA = 0
Note:
Figure 17-4. SPI Transfer Format with CPHA = 1
Note:
96
Serial Clock Timing
*Not defined but normally MSB of character just received.
*Not defined but normally LSB of previously transmitted character.
(FOR REFERENCE)
AT89LP428/828
(FROM MASTER)
SCK (CPOL = 0)
SCK (CPOL = 1)
SS (TO SLAVE)
(FROM SLAVE)
SCK CYCLE #
MOSI
MISO
The TSCK, CPHA, CPOL and SPR bits in SPCR control the shape and rate of SCK. The two
SPR bits provide four possible bit clock rates when the SPI is in master mode. The TSCK bit
also allows a timer-generated bit rate. In slave mode, the SPI will operate at the rate of the
incoming SCK as long as it does not exceed the maximum bit rate. There are also four possible
combinations of SCK phase and polarity with respect to the serial data. CPHA and CPOL deter-
mine which format is used for transmission. The SPI data transfer formats are shown in
17-3 and
SPR should not be modified while the interface is enabled, and the master device should be
enabled before selecting the slave device(s).
*
17-4. To prevent glitches on SCK from disrupting the interface, CPHA, CPOL, and
MSB
MSB
1
2
6
6
3
5
5
4
4
4
5
3
3
6
2
2
7
1
1
8
LSB
LSB
3654A–MICRO–8/09
Figures

Related parts for AT89LP428-20AU