AT90PWM3B-16SUR Atmel, AT90PWM3B-16SUR Datasheet - Page 168
![MCU AVR 8K FLASH 16MHA 32SOIC](/photos/7/29/72992/313-32-soic_sml.jpg)
AT90PWM3B-16SUR
Manufacturer Part Number
AT90PWM3B-16SUR
Description
MCU AVR 8K FLASH 16MHA 32SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM3B-16SUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.25.15 PSC n Input B Control Register – PFRCnB
168
AT90PWM2/3/2B/3B
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The
2 blocks are identical, so they are configured on the same way.
• Bit 7 – PCAEnx : PSC n Capture Enable Input Part x
Writing this bit to one enables the capture function when external event occurs on input selected
as input for Part x (see PISELnx bit in the same register).
• Bit 6 – PISELnx : PSC n Input Select for Part x
Clear this bit to select PSCINn as input of Fault/Retrigger block x.
Set this bit to select Comparator n Output as input of Fault/Retrigger block x.
• Bit 5 –PELEVnx : PSC n Edge Level Selector of Input Part x
When this bit is clear, the falling edge or low level of selected input generates the significative
event for retrigger or fault function .
When this bit is set, the rising edge or high level of selected input generates the significative
event for retrigger or fault function.
• Bit 4 – PFLTEnx : PSC n Filter Enable on Input Part x
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the retrigger pin is filtered. The filter function requires four successive
equal valued samples of the retrigger pin for changing its output. The Input Capture is therefore
delayed by four oscillator cycles when the noise canceler is enabled.
• Bit 3:0 – PRFMnx3:0: PSC n Fault Mode
These four bits define the mode of operation of the Fault or Retrigger functions.
(see PSC Functional Specification for more explanations)
Table 16-17. Level Sensitivity and Fault Mode Operation
Bit
Read/Write
Initial Value
PRFMnx3:0
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
PCAEnB
R/W
7
0
Description
No action, PSC Input is ignored
PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait
PSC Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait
PSC Input Mode 3: Stop signal, Execute Opposite while Fault active
PSC Input Mode 4: Deactivate outputs without changing timing.
PSC Input Mode 5: Stop signal and Insert Dead-Time
PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait.
PSC Input Mode 7: Halt PSC and Wait for Software Action
PSC Input Mode 8: Edge Retrigger PSC
PISELnB
R/W
6
0
PELEVnB
R/W
5
0
PFLTEnB
R/W
4
0
PRFMnB3 PRFMnB2 PRFMnB1 PRFMnB0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
4317J–AVR–08/10
PFRCnB
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