AT90PWM3B-16SUR Atmel, AT90PWM3B-16SUR Datasheet - Page 250

• Manufacturer Part Number: AT90PWM3B-16SUR
• Description: MCU AVR 8K FLASH 16MHA 32SOIC
• Manufacturer: Atmel
• Series: AVR® 90PWM Lightingr

Specifications of AT90PWM3B-16SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 27
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.8.4
21.8.4.1
21.8.4.2
21.8.5
250
AT90PWM2/3/2B/3B
ADC Result Data Registers – ADCH and ADCL
Digital Input Disable Register 0 – DIDR0
ADLAR = 0
ADLAR = 1
Table 21-7.
1.
When an ADC conversion is complete, the conversion results are stored in these two result data
registers.
When the ADCL register is read, the two ADC result data registers can’t be updated until the
ADCH register has also been read.
Consequently, in 10-bit configuration, the ADCL register must be read first before the ADCH.
Nevertheless, to work easily with only 8-bit precision, there is the possibility to left adjust the
result thanks to the ADLAR bit in the ADCSRA register. Like this, it is sufficient to only read
ADCH to have the conversion result.
• Bit 7:0 – ADC7D..ADC0D: ACMP2:1 and ADC7:0 Digital Input Disable
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
ADTS3
1
1
1
1
1
1
For trigger on any PSC event, if the PSC uses the PLL clock, the core must use PLL/4 clock
source.
ADC Auto Trigger Source Selection for amplified conversions
ADTS2
0
0
1
1
1
1
ADC7D
ADC7
ADC9
ADC1
R/W
R
R
R
R
7
0
0
7
0
0
7
0
-
ADC6D
ADC6
ADC8
ADC0
R/W
6
0
R
R
R
R
6
0
0
6
0
0
-
ADTS1
1
1
0
0
1
1
ADC5D
ADC5
ADC7
R/W
R
R
R
R
5
0
5
0
0
5
0
0
-
-
ADC4D
ADTS0
0
1
0
1
0
1
ADC4
ADC6
R/W
R
R
R
R
4
0
4
0
0
4
0
0
-
-
ACMPM
ADC3D
ADC3
ADC5
R/W
R
R
R
R
3
0
0
3
0
0
3
0
-
-
Description
PSC2ASY Event
Reserved
Reserved
Reserved
Reserved
Reserved
ACMP2D
ADC2D
ADC2
ADC4
R/W
R
R
R
R
2
0
2
0
0
2
0
0
-
-
ADC1D
ADC9
ADC1
ADC3
R/W
R
R
R
R
1
0
0
1
0
0
1
0
-
(1)
ADC0D
ADC8
ADC0
ADC2
R/W
R
R
R
R
0
0
0
0
0
0
0
0
-
4317J–AVR–08/10
ADCH
ADCL
ADCH
ADCL
DIDR0