AT90PWM3B-16SUR Atmel, AT90PWM3B-16SUR Datasheet - Page 36
![MCU AVR 8K FLASH 16MHA 32SOIC](/photos/7/29/72992/313-32-soic_sml.jpg)
AT90PWM3B-16SUR
Manufacturer Part Number
AT90PWM3B-16SUR
Description
MCU AVR 8K FLASH 16MHA 32SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM3B-16SUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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7.6.2
7.7
7.8
36
128 kHz Internal Oscillator
External Clock
AT90PWM2/3/2B/3B
PLL Control and Status Register – PLLCSR
Figure 7-5.
• Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM2/2B/3/3B and always read as zero.
• Bit 2 – PLLF: PLL Factor
The PLLF bit is used to select the division factor of the PLL.
If PLLF is set, the PLL output is 64Mhz.
If PLLF is clear, the PLL output is 32Mhz.
• Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is
started as PLL reference clock. If PLL is selected as a system clock source the value for this bit
is always 1.
• Bit 0 – PLOCK: PLL Lock Detector
When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable
CLK
The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-
quency is nominal at 3V and 25°C. This clock is used by the Watchdog Oscillator.
To drive the device from an external clock source, XTAL1 should be driven as shown in
7-6. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.
Bit
$29 ($29)
Read/Write
Initial Value
PLL
XTAL1
XTAL2
for PSC. After the PLL is enabled, it takes about 100 ms for the PLL to lock.
RC OSCILLATOR
OSCCAL
8 MHz
PCK Clocking System AT90PWM2B/3B
OSCILLATORS
R
7
–
0
R
6
–
0
CKSEL3..0
R
5
–
0
DIVIDE
BY 8
R
4
–
0
PLLE
PLL
64x
R
3
–
0
Detector
Lock
DIVIDE
DIVIDE
PLLF
PLLF
BY 2
BY 4
R/W
2
0
PLLE
R/W
0/1
1
PLOCK
CLK
PLOCK
R
0
0
CK
PLL
SOURCE
4317J–AVR–08/10
PLLCSR
Figure
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