AT90PWM3B-16SUR Atmel, AT90PWM3B-16SUR Datasheet - Page 171
![MCU AVR 8K FLASH 16MHA 32SOIC](/photos/7/29/72992/313-32-soic_sml.jpg)
AT90PWM3B-16SUR
Manufacturer Part Number
AT90PWM3B-16SUR
Description
MCU AVR 8K FLASH 16MHA 32SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM3B-16SUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.26.4
16.26.5
16.26.6
16.26.7
4317J–AVR–08/10
PSC2 Interrupt Mask Register – PIM2
PSC0 Interrupt Flag Register – PIFR0
PSC1 Interrupt Flag Register – PIFR1
PSC2 Interrupt Flag Register – PIFR2
Bit
Read/Write
Initial Value
• Bit 5 – PSEIEn : PSC n Synchro Error Interrupt Enable
When this bit is set, the PSEIn bit (if set) generate an interrupt.
• Bit 4 – PEVEnB : PSC n External Event B Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
B generates also an interrupt.
• Bit 3 – PEVEnA : PSC n External Event A Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block
A generates also an interrupt.
• Bit 0 – PEOPEn : PSC n End Of Cycle Interrupt Enable
When this bit is set, an interrupt is generated when PSC reaches the end of the whole cycle.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• Bit 7 – POACnB : PSC n Output B Activity (not implemented on AT90PWM2/3)
This bit is set by hardware each time the output PSCOUTn1 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
This feature is useful to detect that a PSC output doesn’t change due to a freezen external input
signal.
• Bit 6 – POACnA : PSC n Output A Activity (not implemented on AT90PWM2/3)
This bit is set by hardware each time the output PSCOUTn0 changes from 0 to 1 or from 1 to 0.
Must be cleared by software by writing a one to its location.
POAC0B
POAC1B
POAC2B
R
R
R
R
7
0
7
0
7
0
7
0
-
POAC0A
POAC1A
POAC2A
R
R
R
R
6
0
6
0
6
0
6
0
-
PSEIE2
PSEI0
PSEI1
PSEI2
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
PEVE2B
PEV0B
PEV1B
PEV2B
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
PEVE2A
PEV0A
PEV1A
PEV2A
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
AT90PWM2/3/2B/3B
PRN01
PRN11
PRN21
R
R
R
R
2
0
2
0
2
0
2
0
-
PRN00
PRN10
PRN20
R
R
R
R
1
0
1
0
1
0
1
0
-
PEOPE2
PEOP2
PEOP1
PEOP2
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
PIFR0
PIFR1
PIFR2
PIM2
171
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