AT90PWM3B-16SUR Atmel, AT90PWM3B-16SUR Datasheet - Page 20
![MCU AVR 8K FLASH 16MHA 32SOIC](/photos/7/29/72992/313-32-soic_sml.jpg)
AT90PWM3B-16SUR
Manufacturer Part Number
AT90PWM3B-16SUR
Description
MCU AVR 8K FLASH 16MHA 32SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM3B-16SUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
27
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 11x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
32-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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6.3
6.3.1
6.3.2
20
EEPROM Data Memory
AT90PWM2/3/2B/3B
EEPROM Read/Write Access
The EEPROM Address Registers – EEARH and EEARL
Figure 3. On-chip Data SRAM Access Cycles
The AT90PWM2/2B/3/3B contains 512 bytes of data EEPROM memory. It is organized as a
separate data space, in which single bytes can be read and written. The EEPROM has an
endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the
CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM
Data Register, and the EEPROM Control Register.
For a detailed description of SPI and Parallel data downloading to the EEPROM, see
Downloading” on page
mands” on page 282
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
lets the user software detect when the next byte can be written. If the user code contains instruc-
tions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, V
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
For details on how to avoid problems in these situations
tion” on page 25.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
Bit
CC
is likely to rise or fall slowly on power-up/down. This causes the device for some
15
–
Address
clk
Data
Data
WR
CPU
RD
respectively.
14
293, and
–
Compute Address
13
–
“Parallel Programming Parameters, Pin Mapping, and Com-
T1
Memory Access Instruction
12
–
11
–
Table
Address valid
T2
10
seeSee “Preventing EEPROM Corrup-
–
6-2. A self-timing function, however,
9
–
Next Instruction
EEAR8
8
T3
EEARH
4317J–AVR–08/10
“Serial
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