PIC18F26K20-E/ML Microchip Technology, PIC18F26K20-E/ML Datasheet - Page 278

• Manufacturer Part Number: PIC18F26K20-E/ML
• Description: IC PIC MCU FLASH 32KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.84375KB
• Cpu Speed: 64MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Details

PIC18F2XK20/4XK20
FIGURE 20-3:
DS41303E-page 276
FIGURE 20-2:
FVR
C1RSEL
CV
FVR
CV
C2RSEL
REF
REF
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C12IN0-
C12IN1-
C12IN2-
C12IN3-
C1IN+
C2IN+
C1CH<1:0>
C2CH<1:0>
0
1
0
1
MUX
MUX
COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM
COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM
C1V
C2V
C1R
C2R
0
1
2
3
0
1
REF
REF
Note 1:
0
1
MUX
0
1
2
3
2
MUX
Note 1:
MUX
2
MUX
2:
3:
4:
2:
3:
4:
C2V
C2V
When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
Output shown for reference only. See I/O port pin block diagram for more detail.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
C1V
C1V
When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate.
Output shown for reference only. See I/O port pin block diagram for more detail.
Q1 and Q3 are phases of the four-phase system clock (F
Q1 is held high during Sleep mode.
C2SP
IN
IN
C1SP
IN
IN
-
+
-
+
C2
+
-
C2ON
C1
C1ON
C2POL
Preliminary
(1)
C1POL
(1)
Q3*RD_CM2CON0
Q3*RD_CM1CON0
Q1
Q1
NRESET
C2OUT
D
EN
Reset
D
EN
C1OUT
Q
Q
D
EN
CL
D
EN
CL
Q
Q
© 2009 Microchip Technology Inc.
OSC
RD_CM2CON0
OSC
RD_CM1CON0
C2OE
).
To PWM Logic
).
To PWM Logic
C1OE
Data Bus
Set C2IF
C2OUT pin
Data Bus
Set C1IF
C1OUT pin
To
To
(2)
(2)