PIC18F26K20-E/ML Microchip Technology, PIC18F26K20-E/ML Datasheet - Page 93

• Manufacturer Part Number: PIC18F26K20-E/ML
• Description: IC PIC MCU FLASH 32KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.84375KB
• Cpu Speed: 64MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Details

6.3
The TBLRD instruction retrieves data from program
memory and places it into data RAM. Table reads from
program memory are performed one byte at a time.
TBLPTR points to a byte address in program space.
Executing TBLRD places the byte pointed to into
TABLAT. In addition, TBLPTR can be modified
automatically for the next table read operation.
FIGURE 6-4:
EXAMPLE 6-1:
© 2009 Microchip Technology Inc.
READ_WORD
Reading the Flash Program
Memory
Instruction Register
MOVLW
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
TBLRD*+
MOVF
MOVWF
TBLRD*+
MOVFW
MOVF
(IR)
READS FROM FLASH PROGRAM MEMORY
READING A FLASH PROGRAM MEMORY WORD
CODE_ADDR_UPPER
TBLPTRU
CODE_ADDR_HIGH
TBLPTRH
CODE_ADDR_LOW
TBLPTRL
TABLAT, W
WORD_EVEN
TABLAT, W
WORD_ODD
(Even Byte Address)
FETCH
Program Memory
Preliminary
; Load TBLPTR with the base
; address of the word
; read into TABLAT and increment
; get data
; read into TABLAT and increment
; get data
(Odd Byte Address)
The internal program memory is typically organized by
words. The Least Significant bit of the address selects
between the high and low bytes of the word. Figure 6-4
shows the interface between the internal program
memory and the TABLAT.
PIC18F2XK20/4XK20
TBLPTR = xxxxx1
TBLRD
Read Register
TABLAT
TBLPTR = xxxxx0
DS41303E-page 91