PIC18F26K20-E/ML Microchip Technology, PIC18F26K20-E/ML Datasheet - Page 51

• Manufacturer Part Number: PIC18F26K20-E/ML
• Description: IC PIC MCU FLASH 32KX16 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/ML

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC18
• No. Of I/o's: 25
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.84375KB
• Cpu Speed: 64MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: CCP, ECCP, EUSART, I2C, MSSP, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Package: 28QFN EP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 64 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
• Lead Free Status / Rohs Status: Details

4.0
The
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
© 2009 Microchip Technology Inc.
OSC1
MCLR
V
Note 1: See Table 4-2 for time-out situations.
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power-managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
PIC18F2XK20/4XK20
RESET
2: PWRT and OST counters are reset by POR and BOR. See Sections 4.3 and 4.4.
LFINTOSC
Instruction
RESET
OST/PWRT
Pointer
32 μs
Stack
( )_IDLE
Brown-out
Time-out
Detect
Sleep
WDT
Reset
V
DD
OST
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
(2)
BOREN
(2)
POR
1024 Cycles
devices
65.5 ms
differentiate
Preliminary
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0
Section 4.4 “Brown-out Reset (BOR)”.
PIC18F2XK20/4XK20
RCON Register
“Interrupts”.
S
R
BOR
DS41303E-page 49
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(1)
in