PIC18F26K20-E/ML Microchip Technology, PIC18F26K20-E/ML Datasheet - Page 388

IC PIC MCU FLASH 32KX16 28QFN

PIC18F26K20-E/ML

Manufacturer Part Number
PIC18F26K20-E/ML
Description
IC PIC MCU FLASH 32KX16 28QFN
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr

Specifications of PIC18F26K20-E/ML

Core Size
8-Bit
Program Memory Size
64KB (32K x 16)
Core Processor
PIC
Speed
48MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
1024Byte
Ram Memory Size
3.84375KB
Cpu Speed
64MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
CCP, ECCP, EUSART, I2C, MSSP, SPI
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Package
28QFN EP
Device Core
PIC
Family Name
PIC18
Maximum Speed
64 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPAC164322 - MODULE SOCKET MPLAB PM3 28/44QFN
Lead Free Status / Rohs Status
 Details
PIC18F2XK20/4XK20
FIGURE 26-11:
TABLE 26-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4XK20)
DS41303E-page 386
62
63
64
65
66
Param.
No.
Note:
RD7:RD0
RE1/WR
RE0/RD
RE2/CS
TdtV2wrH
TwrH2dtI
TrdL2dtV
TrdH2dtI
TibfINH
Symbol
Refer to Figure 26-4 for load conditions.
PARALLEL SLAVE PORT TIMING (PIC18F4XK20)
Data In Valid before WR ↑ or CS ↑
(setup time)
WR ↑ or CS ↑ to Data–In Invalid (hold time)
RD ↓ and CS ↓ to Data–Out Valid
RD ↑ or CS ↓ to Data–Out Invalid
Inhibit of the IBF Flag bit being Cleared from
WR ↑ or CS ↑
64
Characteristic
65
Preliminary
Min
20
20
10
3 T
Max
62
80
30
CY
© 2009 Microchip Technology Inc.
Units
63
ns
ns
ns
ns
Conditions

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