ATMEGA8L-8PU Atmel, ATMEGA8L-8PU Datasheet - Page 213

IC AVR MCU 8K 8MHZ 3V 28DIP

ATMEGA8L-8PU

Manufacturer Part Number
ATMEGA8L-8PU
Description
IC AVR MCU 8K 8MHZ 3V 28DIP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA8L-8PU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Interface Type
SPI/TWI/USART
Total Internal Ram Size
1KB
# I/os (max)
23
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
2.7V
On-chip Adc
6-chx10-bit
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
28
Package Type
PDIP
Processor Series
ATMEGA8x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
Controller Family/series
AVR MEGA
No. Of I/o's
23
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATSTK600-DIP40 - STK600 SOCKET/ADAPTER 40-PDIP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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ATmega8 Boot Loader
Parameters
2486Z–AVR–02/11
In
programming are given.
Table 82. Boot Size Configuration
Note:
BOOTSZ1
Table 82
Return:
ready yet
Do_spm:
Wait_spm:
Wait_ee:
1
1
0
0
; return to RWW section
; verify that RWW section is safe to read
in
sbrs temp1, RWWSB
ret
; re-enable the RWW section
ldi
rcallDo_spm
rjmp Return
; check for previous SPM complete
in
sbrc temp1, SPMEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
cli
; check that no EEPROM write access is present
sbic EECR, EEWE
rjmp Wait_ee
; SPM timed sequence
out
spm
; restore SREG (to enable interrupts if originally enabled)
out
ret
The different BOOTSZ Fuse configurations are shown in
temp1, SPMCR
spmcrval, (1<<RWWSRE) | (1<<SPMEN)
temp1, SPMCR
temp2, SREG
SPMCR, spmcrval
SREG, temp2
through
BOOTSZ0
1
0
1
0
Table 84 on page
Boot
Size
128
words
256
words
512
words
1024
words
Pages
16
32
4
8
214, the parameters used in the description of the self
Application
Flash
Section
0x000 -
0xF7F
0x000 -
0xEFF
0x000 -
0xDFF
0x000 -
0xBFF
; If RWWSB is set, the RWW section is not
Boot
Loader
Flash
Section
0xF80 -
0xFFF
0xF00 -
0xFFF
0xE00 -
0xFFF
0xC00 -
0xFFF
Figure 102 on page 204
End
Application
Section
0xF7F
0xEFF
0xDFF
0xBFF
ATmega8(L)
Boot Reset
Address
(Start Boot
Loader
Section)
0xF80
0xF00
0xE00
0xC00
213

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