AT32UC3B0256-A2UR Atmel, AT32UC3B0256-A2UR Datasheet - Page 207

MCU AVR32 256K FLASH 64-TQFP

AT32UC3B0256-A2UR

Manufacturer Part Number
AT32UC3B0256-A2UR
Description
MCU AVR32 256K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3B0256-A2UR

Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Package
64TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
44
Interface Type
I2S/SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B0256-A2UR
Manufacturer:
Atmel
Quantity:
10 000
18.8.1
Name:
Access Type:
Offset:
Reset Value:
• LASTXFER: Last Transfer
• SWRST: SPI Software Reset
• SPIDIS: SPI Disable
• SPIEN: SPI Enable
32059K–03/2011
SWRST
31
23
15
7
0: No effect.
1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows
to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has
completed.
0: No effect.
1: Reset the SPI. A software-triggered hardware reset of the SPI interface is performed.
The SPI is in slave mode after software reset.
Peripheral DMA Controller
0: No effect.
1: Disables the SPI.
As soon as SPIDIS is set, SPI finishes its tranfer.
All pins are set in input mode and no data is received or transmitted.
If a transfer is in progress, the transfer is finished before the SPI is disabled.
If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled.
0: No effect.
1: Enables the SPI to transfer and receive data.
Control Register
30
22
14
CR
Write-only
0x00
0x00000000
6
channels are not affected by software reset.
29
21
13
5
28
20
12
4
27
19
11
3
26
18
10
2
SPIDIS
25
17
9
1
AT32UC3B
LASTXFER
SPIEN
24
16
8
0
-
207

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