AT32UC3B0256-A2UR Atmel, AT32UC3B0256-A2UR Datasheet - Page 587
![MCU AVR32 256K FLASH 64-TQFP](/photos/6/81/68127/313-64-vqfp_sml.jpg)
AT32UC3B0256-A2UR
Manufacturer Part Number
AT32UC3B0256-A2UR
Description
MCU AVR32 256K FLASH 64-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet
1.AT32UC3B1512-Z1UT.pdf
(692 pages)
Specifications of AT32UC3B0256-A2UR
Package / Case
64-TQFP, 64-VQFP
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Operating Temperature
-40°C ~ 85°C
Speed
60MHz
Number Of I /o
44
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32K x 8
Program Memory Size
256KB (256K x 8)
Data Converters
A/D 8x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Core Size
32-Bit
Package
64TQFP
Device Core
AVR32
Family Name
AT32
Maximum Speed
60 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
44
Interface Type
I2S/SPI/TWI/USART/USB
On-chip Adc
8-chx10-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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27.3.4.1
27.3.4.2
32059K–03/2011
Debug Communication Channel
breakpoints
Figure 27-2. JTAG-based Debugger
The Debug Communication Channel (DCC) consists of a pair OCD registers with associated
handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange
data between the CPU and the JTAG master, both runtime as well as in debug mode.
One of the most fundamental debug features is the ability to halt the CPU, to examine registers
and the state of the system. This is accomplished by breakpoints, of which many types are
available:
When a breakpoint triggers, the CPU enters debug mode, and the D bit in the Status Register is
set. This is a privileged mode with dedicated return address and return status registers. All privi-
leged instructions are permitted. Debug mode can be entered as either OCD mode, running
instructions from JTAG, or monitor mode, running instructions from program memory.
• Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU
• Program breakpoints halt the CPU when a specific address in the program is executed.
• Data breakpoints halt the CPU when a specific memory address is read or written, allowing
• Software breakpoints halt the CPU when the breakpoint instruction is executed.
immediately.
variables to be watched.
JTAG-based
debug tool
10-pin IDC
AVR32
JTAG
PC
AT32UC3B
587
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