AT32UC3B0256-A2UR Atmel, AT32UC3B0256-A2UR Datasheet - Page 297

• Manufacturer Part Number: AT32UC3B0256-A2UR
• Description: MCU AVR32 256K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-A2UR

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Package: 64TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 44
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

21. Universal Synchronous Asynchronous Receiver Transmitter (USART)
21.1
21.2
32059K–03/2011
Features
Overview
Rev: 4.0.0.5
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The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full
duplex universal synchronous asynchronous serial link. Data frame format is widely programma-
ble (data length, parity, number of stop bits) to support a maximum of standards. The receiver
implements parity error, framing error and overrun error detection. The receiver time-out enables
handling variable-length frames and the transmitter timeguard facilitates communications with
slow remote devices. Multidrop communications are also supported through address bit han-
dling in reception and transmission.
The USART features three test modes: remote loopback, local loopback and automatic echo.
The USART supports specific operating modes providing interfaces on RS485 and SPI buses,
with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem
ports. The hardware handshaking feature enables an out-of-band flow control by automatic
management of the pins RTS and CTS.
The USART supports the connection to the Peripheral DMA Controller, which enables data
transfers to the transmitter and from the receiver. The Peripheral DMA Controller provides
chained buffer management without any intervention of the processor.
Configurable baud rate generator
5- to 9-bit full-duplex synchronous or asynchronous serial communication
RS485 with line driver control
ISO7816, T=0 and T=1 protocols for Interfacing with smart cards
IrDA modulation and demodulation
SPI Mode
Test Modes
Supports two Peripheral DMA Controller channels
– 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode
– Parity generation and error detection
– Framing- and overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– Receiver frequency over-sampling by 8 or 16 times
– Optional RTS-CTS hardware handshaking
– Optional DTR-DSR-DCD-RI modem signal management
– Receiver Time-out and transmitter Timeguard
– Optional Multidrop mode with address generation and detection
– NACK handling
– Error counter with configurable repetition and iteration limits
– Communication at up to 115.2Kbit/s
– Master or slave
– Configurable Serial Clock phase and polarity
– CLK SPI Serial Clock frequency up to a quarter of the CLK_USART internal clock frequency
– Automatic Echo, Remote- and Local Loopback
– Buffer transfers without processor intervention
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