AT32UC3B0256-A2UR Atmel, AT32UC3B0256-A2UR Datasheet - Page 512

• Manufacturer Part Number: AT32UC3B0256-A2UR
• Description: MCU AVR32 256K FLASH 64-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0256-A2UR

• Package / Case: 64-TQFP, 64-VQFP
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Program Memory Size: 256KB (256K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Package: 64TQFP
• Device Core: AVR32
• Family Name: AT32
• Maximum Speed: 60 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 44
• Interface Type: I2S/SPI/TWI/USART/USB
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

23.7.8
Name:
Access Type:
Offset:
Reset Value:
Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
• MTIOB: TIOB Mirror
• MTIOA: TIOA Mirror
• CLKSTA: Clock Enabling Status
• ETRGS: External Trigger Status
• LDRBS: RB Loading Status
• LDRAS: RA Loading Status
• CPCS: RC Compare Status
32059K–03/2011
ETRGS
31
23
15
7
-
-
-
1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven
high.
0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven
low.
1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven
high.
0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven
low.
1: This bit is set when the clock is enabled.
0: This bit is cleared when the clock is disabled.
1: This bit is set when an external trigger has occurred.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RC Compare has occurred.
0: This bit is cleared when the SR register is read.
Channel Status Register
LDRBS
30
22
14
6
-
-
-
SR
Read-only
0x20 + n * 0x40
0x00000000
LDRAS
29
21
13
5
-
-
-
CPCS
28
20
12
4
-
-
-
CPBS
27
19
11
3
-
-
-
MTIOB
CPAS
26
18
10
2
-
-
LOVRS
MTIOA
25
17
9
1
-
-
AT32UC3B
CLKSTA
COVFS
24
16
8
0
-
-
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