AT91SAM9260B-QU Atmel, AT91SAM9260B-QU Datasheet - Page 162

IC ARM9 MCU 208-PQFP

AT91SAM9260B-QU

Manufacturer Part Number
AT91SAM9260B-QU
Description
IC ARM9 MCU 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM9260B-QU

Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
96
Interface Type
EBI/Ethernet/SPI/TWI/UART/USART/USB
On-chip Adc
4-chx10-bit
Number Of Timers
6
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Ram Size
8 KB
Maximum Clock Frequency
180 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
Minimum Operating Temperature
- 40 C
Cpu Family
AT91
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
8KB
# I/os (max)
96
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
For Use With
AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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20.4
20.4.1
Figure 20-1. SMC Connections to Static Memory Devices
20.5
20.5.1
162
Application Example
Product Dependencies
AT91SAM9260
Hardware Interface
I/O Lines
Static Memory
Controller
A1/NWR2/NBS2
NWR1/NBS1
NWR3/NBS3
NWR0/NWE
A2 - A25
A0/NBS0
D0-D31
NCS0
NCS1
NCS2
NCS3
NCS4
NCS5
NCS6
NCS7
The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO
lines. The programmer must first program the PIO controller to assign the Static Memory Con-
troller pins to their peripheral function. If I/O Lines of the SMC are not used by the application,
they can be used for other purposes by the PIO Controller.
A1/NWR2/NBS2
NWR0/NWE
NRD
NRD
D16 - D23
D0 - D7
D0 - D7
CS
OE
WE
D0 - D7
CS
OE
WE
128K x 8
128K x 8
SRAM
SRAM
A0 - A16
A0 - A16
A2 - A18
A2 - A18
NWR1/NBS1
NWR3/NBS3
D24-D31
D8-D15
NRD
NRD
OE
WE
OE
WE
D0-D7
CS
D0-D7
CS
128K x 8
128K x 8
SRAM
SRAM
A0 - A16
A0 - A16
A2 - A18
A2 - A18
6221I–ATARM–17-Jul-09

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