AT91SAM9260B-QU Atmel, AT91SAM9260B-QU Datasheet - Page 39

• Manufacturer Part Number: AT91SAM9260B-QU
• Description: IC ARM9 MCU 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Package: 208PQFP
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/UART/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT91
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 96
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6221I–ATARM–17-Jul-09
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bits[31:28]).
Table 10-2
Table 10-2.
Mnemonic
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
LDRSH
SMULL
SMLAL
LDRSB
LDRBT
LDRH
LDRB
LDRT
MOV
CMP
MSR
SWP
MCR
ADD
SUB
RSB
AND
EOR
MUL
LDM
CDP
LDR
LDC
TST
BX
B
gives the ARM instruction mnemonic list.
ARM Instruction Mnemonic List
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
Signed Long Multiply
Accumulate
Move to Status Register
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Load Register Byte with
Translation
Load Register with Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Coprocessor Data Processing
Branch
Mnemonic
UMULL
UMLAL
STRBT
SWPB
STRH
STRB
STRT
MVN
CMN
ORR
MRS
MRC
ADC
SBC
RSC
TEQ
MLA
STR
STM
STC
SWI
BIC
BL
Operation
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply
Accumulate
Move From Status Register
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
Store Register Byte with
Translation
Store Register with Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
AT91SAM9260
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