ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 200

• Manufacturer Part Number: ATMEGA2560V-8AU
• Description: IC AVR MCU 256K 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2560V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• A/d Inputs: 16-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 86
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Timers: 2-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Package: 100TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.1
20.1.1
20.1.2
20.1.3
2549M–AVR–09/10
SS Pin Functionality
Slave Mode
Master Mode
Data Modes
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin
is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the following
actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master
mode.
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in
20-3 on page 201
opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is
clearly seen by summarizing
Table 20-2.
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
set, the interrupt routine will be executed.
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
CPOL Functionality
and
Figure 20-4 on page
Table 20-3 on page 202
ATmega640/1280/1281/2560/2561
Sample (Falling)
Sample (Rising)
Leading Edge
Setup (Falling)
Setup (Rising)
201. Data bits are shifted out and latched in on
and
Table 20-4 on page 202
Sample (Falling)
Sample (Rising)
Setup (Falling)
Setup (Rising)
Trailing eDge
in
SPI Mode
Table
0
1
2
3
Figure
20-2.
200