ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 275

IC AVR MCU 256K 8MHZ 100TQFP

ATMEGA2560V-8AU

Manufacturer Part Number
ATMEGA2560V-8AU
Description
IC AVR MCU 256K 8MHZ 100TQFP
Manufacturer
Atmel
Series
AVR® ATmegar

Specifications of ATMEGA2560V-8AU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
86
Program Memory Size
256KB (128K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-TQFP, 100-VQFP
Processor Series
ATMEGA256x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
8 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
86
Number Of Timers
6
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
A/d Inputs
16-Channel, 10-Bit
Cpu Speed
8 MIPS
Eeprom Memory
4K Bytes
Input Output
86
Interface
2-Wire/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
100-pin TQFP
Programmable Memory
256K Bytes
Timers
2-8-bit, 4-16-bit
Voltage, Range
1.8-5.5 V
Package
100TQFP
Device Core
AVR
Family Name
ATmega
Maximum Speed
8 MHz
For Use With
ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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25. ADC – Analog to Digital Converter
25.1
2549M–AVR–09/10
Features
The ATmega640/1280/1281/2560/2561 features a 10-bit successive approximation ADC. The
ADC is connected to an 8/16-channel Analog Multiplexer which allows eight/sixteen single-
ended voltage inputs constructed from the pins of Port F and Port K. The single-ended voltage
inputs refer to 0V (GND).
The device also supports 16/32 differential voltage input combinations. Four of the differential
inputs (ADC1 & ADC0, ADC3 & ADC2, ADC9 & ADC8 and ADC11 & ADC10) are equipped with
a programmable gain stage, providing amplification steps of 0 dB (1×), 20 dB (10×) or 46 dB
(200×) on the differential input voltage before the ADC conversion. The 16 channels are split in
two sections of 8 channels where in each section seven differential analog input channels share
a common negative terminal (ADC1/ADC9), while any other ADC input in that section can be
selected as the positive input terminal. If 1× or 10× gain is used, 8 bit resolution can be
expected. If 200× gain is used, 7 bit resolution can be expected.
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in
on page
The ADC has a separate analog supply voltage pin, AVCC. AVCC must not differ more than
±0.3V from V
pin.
Internal reference voltages of nominally 1.1V, 2.56V or AVCC are provided On-chip. The voltage
reference may be externally decoupled at the AREF pin by a capacitor for better noise
performance.
The Power Reduction ADC bit, PRADC, in
must be disabled by writing a logical zero to enable the ADC.
10-bit Resolution
1 LSB Integral Non-linearity
±2 LSB Absolute Accuracy
13 µs - 260 µs Conversion Time
Up to 76.9 kSPS (Up to 15 kSPS at Maximum Resolution)
16 Multiplexed Single Ended Input Channels
14 Differential input channels
4 Differential Input Channels with Optional Gain of 10× and 200×
Optional Left Adjustment for ADC Result Readout
0V - V
2.7V - V
Selectable 2.56V or 1.1V ADC Reference Voltage
Free Running or Single Conversion Mode
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
CC
276.
CC
ADC Input Voltage Range
Differential ADC Voltage Range
CC
. See the paragraph
ATmega640/1280/1281/2560/2561
“ADC Noise Canceler” on page 283
“PRR0 – Power Reduction Register 0” on page 56
on how to connect this
Figure 25-1
275

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