ATMEGA2560V-8AU Atmel, ATMEGA2560V-8AU Datasheet - Page 220

• Manufacturer Part Number: ATMEGA2560V-8AU
• Description: IC AVR MCU 256K 8MHZ 100TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA2560V-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 86
• Program Memory Size: 256KB (128K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Processor Series: ATMEGA256x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 8 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 86
• Number Of Timers: 6
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• A/d Inputs: 16-Channel, 10-Bit
• Cpu Speed: 8 MIPS
• Eeprom Memory: 4K Bytes
• Input Output: 86
• Interface: 2-Wire/SPI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Timers: 2-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Package: 100TQFP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 8 MHz
• For Use With: ATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK503 - STARTER KIT AVR EXP MODULE 100PATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.7.3
2549M–AVR–09/10
Asynchronous Operational Range
Figure 21-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 21-2 on page
frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
R
slow
mode.
for Double Speed mode.
S
receiver baud rate. R
accepted in relation to the receiver baud rate.
Sum of character size and parity size (D = 5 to 10 bit).
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
First sample number used for majority voting. S
Middle sample number used for majority voting. S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
=
M
= 5 for Double Speed mode.
------------------------------------------ -
S 1
–
Figure
221) base frequency, the Receiver will not be able to synchronize the
(
D
+
1
1
+
D S ⋅
1
2
21-7. For Double Speed mode the first low level must be delayed to
)S
+
3
2
S
ATmega640/1280/1281/2560/2561
F
4
fast
5
3
is the ratio of the fastest incoming data rate that can be
6
7
4
8
STOP 1
9
5
10
R
fast
(A)
0/1
6
=
0/1
F
-----------------------------------
(
= 8 for normal speed and S
D
(B)
0/1
0/1
(
+
D
M
1
+
= 9 for normal speed and
)S
2
)S
+
S
M
(C)
F
220
= 4