P89V662FBC,557 NXP Semiconductors, P89V662FBC,557 Datasheet - Page 65

• Manufacturer Part Number: P89V662FBC,557
• Description: IC 80C51 MCU FLASH 32K 44-TQFP
• Manufacturer: NXP Semiconductors
• Series: 89Vr

Specifications of P89V662FBC,557

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-TQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 36
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89V6x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 622-1001 - USB IN-CIRCUIT PROG 80C51ISP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-2435; 935280832557; P89V662FBC

NXP Semiconductors
Table 54.
P89V660_662_664_3
Product data sheet
Description
External
Interrupt 0
T0
External
Interrupt 1
T1
UART
I
(primary)
PCA
T2
I
(secondary)
SPI
2
2
C-bus
C-bus
Interrupt polling sequence
6.11 Security bits
6.12 Interrupt priority and polling sequence
Interrupt flag
IE0
TF0
IE1
TF1
TI/RI
-
CF/CCFn
TF2, EXF2
-
SPIF
The security bits protects against software piracy and prevents the contents of the flash
from being read by unauthorized parties in Parallel Programmer mode and ISP mode.
Since the end application might need to erase pages and read from the code memory, the
security bits have no effect in IAP mode. However, the security bits’ programmed/erased
state may be read using IAP function calls allowing the end user code to limit access, if
desired. The security bits and their effects are shown in
Note: On this device MOVC instructions executed from external code memory are
disabled from fetching code bytes from internal code memory.
Table 53.
The device supports eight interrupt sources under a four level priority scheme.
summarizes the polling sequence of the supported interrupts. Note that the SPI serial
interface and the UART share the same interrupt vector. (See
Security bit
1
2
3
Vector address Interrupt
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
004BH
Security bit functions
Rev. 03 — 10 November 2008
Description
Write protect. When programmed, prohibits further erasing or
programming, except to program other security bits or a chip erase.
Read protect. When programmed inhibits reading of user code memory.
External execution inhibit. When programmed prevents any execution of
instructions from external code memory.
enable
EX0
ET0
EX1
ET1
ES0
ES1
EC
ET2
ES2
ES3
80C51 with 512 B/1 kB/2 kB RAM, dual I
Interrupt
priority
PX0/H
PT0/H
PX1/H
PT1/H
PS0/H
PS1/H
PPCH
PT2/H
PS2/H
PS3/H
P89V660/662/664
Table
Service
priority
1 (highest)
3
4
5
6
2
8
7
10
9
53.
Figure
32).
© NXP B.V. 2008. All rights reserved.
Wake-up
Power-down
yes
no
yes
no
no
no
no
no
no
no
2
C-bus, SPI
Table 54
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